libarch: interchange: fixed model ports reading

Signed-off-by: Alessandro Comodi <[email protected]>
verilog-to-routing · Oct 26, 2021 · 4712f09 · 4712f09
1 parent e168dc7
commit 4712f09
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Showing 2 changed files with 9 additions and 1 deletion.
diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp
@@ -221,6 +221,14 @@ struct ArchReader {
                                "Model output ports can not have combinational sink ports");
             }
 
+            model_port->min_size = 1;
+            model_port->size = 1;
+            if (port.isBus()) {
+                int s = port.getBus().getBusStart();
+                int e = port.getBus().getBusEnd();
+                model_port->size = std::abs(e - s) + 1;
+            }
+
             port_names.insert(std::pair<std::string, enum PORTS>(model_port->name, dir));
             //Add the port
             if (dir == IN_PORT) {

diff --git a/vpr/test/test_interchange_netlist.cpp b/vpr/test/test_interchange_netlist.cpp
@@ -21,7 +21,7 @@ TEST_CASE("read_interchange_netlist", "[vpr]") {
     std::vector<t_physical_tile_type> physical_tile_types;
     std::vector<t_logical_block_type> logical_block_types;
 
-    FPGAInterchangeReadArch(kArchFile, &arch, physical_tile_types, logical_block_types);
+    FPGAInterchangeReadArch(kArchFile, /*timing_enabled=*/true, &arch, physical_tile_types, logical_block_types);
 
     vpr_setup.user_models = arch.models;
     vpr_setup.library_models = arch.model_library;