add missing expected tags

verilog-to-routing · Jul 16, 2024 · 639ee62 · 639ee62
1 parent 5a9df1f
commit 639ee62
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diff --git a/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp b/libs/libarchfpga/src/read_xml_arch_file_noc_tag.cpp
@@ -228,7 +228,7 @@ static void process_mesh_topology(pugi::xml_node mesh_topology_tag,
     constexpr int ATTRIBUTE_CONVERSION_FAILURE = -1;
 
     // a list of attributes that should be found for the mesh tag
-    std::vector<std::string> expected_router_attributes = {"startx", "endx", "starty", "endy", "size"};
+    std::vector<std::string> expected_router_attributes = {"startx", "endx", "starty", "endy", "startlayer", "endlayer", "size"};
 
     // verify that only the acceptable attributes were supplied
     pugiutil::expect_only_attributes(mesh_topology_tag, expected_router_attributes, loc_data);

diff --git a/vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_3dnoc_stratixiv_arch.timing.xml b/vtr_flow/arch/multi_die/stratixiv_3d/3d_full_OPIN_inter_die_3dnoc_stratixiv_arch.timing.xml
@@ -4810,7 +4810,6 @@
         </pinlocations>
       </sub_tile>
     </tile>
-    </tile>
     <!-- below we specify a NoC router tile. Not sure about the area (might need to update this) Look into making this block bigger for large number of ports. Also put the master and slave ports on seperate sides-->
     <tile name="noc_router_adapter" width="2" height="2" area="0">
       <sub_tile name="noc_router_adapter">