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Merge branch 'verilog-to-routing:master' into ABC-Update
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navidjafarof authored Sep 14, 2023
2 parents c85f1df + 9066310 commit 80f162f
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Showing 217 changed files with 12,013 additions and 3,002 deletions.
2 changes: 1 addition & 1 deletion dev/subtree_config.xml
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,7 @@
name="yosys"
internal_path="yosys"
external_url="https://github.com/YosysHQ/yosys.git"
default_external_ref="yosys-0.26"/>
default_external_ref="yosys-0.32"/>
<subtree
name="parmys"
internal_path="parmys"
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4 changes: 2 additions & 2 deletions libs/EXTERNAL/CMakeLists.txt
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Expand Up @@ -30,7 +30,7 @@ if (${WITH_PARMYS})
PREFIX "surelog"

GIT_REPOSITORY https://github.com/chipsalliance/Surelog.git
GIT_TAG 900fb2499c7d3f793409999eabee63db513814b4 # yosys-systemverilog release ac4454e-2023-01-13
GIT_TAG v1.71
GIT_PROGRESS TRUE

# setting source, build and install directories
Expand Down Expand Up @@ -61,7 +61,7 @@ if (${WITH_PARMYS})
PREFIX "f4pga-plugins"

GIT_REPOSITORY https://github.com/chipsalliance/yosys-f4pga-plugins.git
GIT_TAG e81b0c14d554fbf9cef14dd33155f441242d5ca2 # yosys-systemverilog release ac4454e-2023-01-13
GIT_TAG v1.20230808
GIT_PROGRESS TRUE

# setting source, build and install directories
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4 changes: 4 additions & 0 deletions libs/librrgraph/src/base/rr_graph_builder.cpp
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Expand Up @@ -29,8 +29,12 @@ void RRGraphBuilder::add_node_to_all_locs(RRNodeId node) {
t_rr_type node_type = node_storage_.node_type(node);
short node_ptc_num = node_storage_.node_ptc_num(node);
short node_layer = node_storage_.node_layer(node);
short node_twist = node_storage_.node_ptc_twist(node);
int node_offset = 0;
for (int ix = node_storage_.node_xlow(node); ix <= node_storage_.node_xhigh(node); ix++) {
for (int iy = node_storage_.node_ylow(node); iy <= node_storage_.node_yhigh(node); iy++) {
node_ptc_num += node_twist * node_offset;
node_offset++;
switch (node_type) {
case SOURCE:
case SINK:
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12 changes: 12 additions & 0 deletions libs/librrgraph/src/base/rr_graph_builder.h
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Expand Up @@ -193,6 +193,12 @@ class RRGraphBuilder {
node_storage_.set_node_layer(id, layer);
}

/** @brief set the ptc twist increment number for TILEABLE rr graphs (for more information see rr_graph_storage.h twist increment comment) */
inline void set_node_ptc_twist_incr(RRNodeId id, int twist){
node_storage_.set_node_ptc_twist_incr(id, twist);
}


/** @brief set_node_pin_num() is designed for logic blocks, which are IPIN and OPIN nodes */
inline void set_node_pin_num(RRNodeId id, int new_pin_num) {
node_storage_.set_node_pin_num(id, new_pin_num);
Expand Down Expand Up @@ -295,6 +301,12 @@ class RRGraphBuilder {
inline void resize_nodes(size_t size) {
node_storage_.resize(size);
}

/** @brief This function resize node ptc twist increment; Since it is only used for tileable rr-graph, we don't put it in general resize function*/
inline void resize_ptc_twist_incr(size_t size){
node_storage_.resize(size);
}

/** @brief This function resize rr_switch to accomidate size RR Switch. */
inline void resize_switches(size_t size) {
rr_switch_inf_.resize(size);
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6 changes: 6 additions & 0 deletions libs/librrgraph/src/base/rr_graph_storage.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -622,6 +622,11 @@ void t_rr_graph_storage::set_node_layer(RRNodeId id, short layer) {
node_layer_[id] = layer;
}

void t_rr_graph_storage::set_node_ptc_twist_incr(RRNodeId id, short twist_incr){
VTR_ASSERT(!node_ptc_twist_incr_.empty());
node_ptc_twist_incr_[id] = twist_incr;
}

void t_rr_graph_storage::set_node_ptc_num(RRNodeId id, int new_ptc_num) {
node_ptc_[id].ptc_.pin_num = new_ptc_num; //TODO: eventually remove
}
Expand Down Expand Up @@ -785,6 +790,7 @@ t_rr_graph_view t_rr_graph_storage::view() const {
vtr::make_const_array_view_id(node_first_edge_),
vtr::make_const_array_view_id(node_fan_in_),
vtr::make_const_array_view_id(node_layer_),
vtr::make_const_array_view_id(node_ptc_twist_incr_),
vtr::make_const_array_view_id(edge_src_node_),
vtr::make_const_array_view_id(edge_dest_node_),
vtr::make_const_array_view_id(edge_switch_));
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