turn on sv test

verilog-to-routing · Dec 10, 2024 · a898031 · a898031
1 parent dd490fb
commit a898031
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Showing 2 changed files with 4 additions and 4 deletions.
diff --git a/.github/workflows/nightly_test.yml b/.github/workflows/nightly_test.yml
@@ -67,7 +67,7 @@ jobs:
           - {test: "vtr_reg_strong_odin",        cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
           - {test: "vtr_reg_system_verilog",     cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""} # Test turned off -> F4PGA conflicts with Yosys (version 42)
           - {test: "odin_reg_strong",            cores: "16", options: "",          cmake: "-DWITH_ODIN=ON",                                               extra_pkgs: ""}
-          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=OFF",                                     extra_pkgs: ""}
+          - {test: "parmys_reg_strong",          cores: "16", options: "",          cmake: "-DYOSYS_F4PGA_PLUGINS=ON",                                     extra_pkgs: ""}
 
     env:
       DEBIAN_FRONTEND: "noninteractive"

diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt
@@ -30,7 +30,7 @@ if (${WITH_PARMYS})
 
     if (${YOSYS_F4PGA_PLUGINS})
 
-set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
+        set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
         set(SURELOG_BINARY_DIR ${SURELOG_SOURCE_DIR}/build)
         set(YOSYS_F4PGA_PLUGINS_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/yosys-f4pga-plugins)
 
@@ -66,7 +66,7 @@ set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
                 DEPENDS yosys
                 )
 
-    # Synlig integration (manages Surelog and UHDM internally)                
+     # Synlig integration (manages Surelog and UHDM internally)                
 
         # Synlig integration (manages Surelog and UHDM internally)
         set(SYNLIG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/synlig)
@@ -115,8 +115,8 @@ set(SURELOG_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/Surelog)
             DEPENDS yosys  # Ensure submodule sync runs before synlig build
         )
 
-        endif ()
     endif ()
+endif ()
 
 
     if (${VTR_ENABLE_CAPNPROTO})