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vaughnbetz authored Aug 15, 2024
2 parents 8554635 + 3ac6d17 commit af31b4d
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110 changes: 110 additions & 0 deletions .github/workflows/nightly_test.yml
Original file line number Diff line number Diff line change
@@ -0,0 +1,110 @@
name: NightlyTest

on:
# We want to run the CI when anything is pushed to master.
# Since master is a protected branch this only happens when a PR is merged.
# This is a double check in case the PR was stale and had some issues.
push:
branches:
- master
paths-ignore: # Prevents from running if only docs are updated
- 'doc/**'
- '**/*README*'
- '**.md'
- '**.rst'
pull_request:
paths-ignore: # Prevents from running if only docs are updated
- 'doc/**'
- '**/*README*'
- '**.md'
- '**.rst'
workflow_dispatch:
schedule:
- cron: '0 0 * * *' # daily

# We want to cancel previous runs for a given PR or branch / ref if another CI
# run is requested.
# See: https://docs.github.com/en/actions/using-jobs/using-concurrency
concurrency:
group: ${{ github.workflow }}-${{ github.event.pull_request.number || github.ref }}
cancel-in-progress: true

env:
# default compiler for all non-compatibility tests
MATRIX_EVAL: "CC=gcc-11 && CXX=g++-11"

jobs:
Run-tests:
# Prevents from running on forks where no custom runners are available
if: ${{ github.repository_owner == 'verilog-to-routing' }}

timeout-minutes: 420

container: ubuntu:jammy

runs-on: [self-hosted, Linux, X64]

strategy:
fail-fast: false
matrix:
include:
- {test: "vtr_reg_nightly_test1", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test2", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test3", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test3_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test4", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test4_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test5", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test6", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test7", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}

env:
DEBIAN_FRONTEND: "noninteractive"

steps:

# TODO: This runnner is running on a self-hosted CPU. In order to upgrade
# to v4, need to upgrade the machine to support node20.
- uses: actions/checkout@v3
with:
submodules: 'true'

- name: Setup
run: stdbuf -i0 -i0 -e0 ./.github/scripts/hostsetup.sh

- name: Install external libraries
run: apt install -y ${{ matrix.extra_pkgs }}
if: ${{ matrix.extra_pkgs }}

- name: Execute test script
run: stdbuf -i0 -o0 -e0 ./.github/scripts/run-vtr.sh
env:
VPR_NUM_WORKERS: 4
VTR_TEST: ${{ matrix.test }}
VTR_TEST_OPTIONS: ${{ matrix.options }}
VTR_CMAKE_PARAMS: ${{ matrix.cmake }}
NUM_CORES: ${{ matrix.cores }}

- name: Upload test results
# If the job was not cancelled, we want to save the result (this includes
# when the job fails). See warning here:
# https://docs.github.com/en/actions/learn-github-actions/expressions#always
if: ${{ !cancelled() }}
# TODO: This runnner is running on a self-hosted CPU. In order to upgrade
# to v4, need to upgrade the machine to support node20.
uses: actions/upload-artifact@v3
with:
name: ${{matrix.test}}_test_results
path: |
**/results*.gz
**/plot_*.svg
**/qor_results*.tar.gz
77 changes: 0 additions & 77 deletions .github/workflows/test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -34,83 +34,6 @@ env:
MATRIX_EVAL: "CC=gcc-11 && CXX=g++-11"

jobs:


Run-tests:
# Prevents from running on forks where no custom runners are available
if: ${{ github.repository_owner == 'verilog-to-routing' }}

timeout-minutes: 420

container: ubuntu:jammy

runs-on: [self-hosted, Linux, X64]

strategy:
fail-fast: false
matrix:
include:
- {test: "vtr_reg_nightly_test1", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test1_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test2", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test2_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test3", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test3_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test4", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test4_odin", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test5", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test6", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_nightly_test7", cores: "16", options: "", cmake: "", extra_pkgs: ""}
- {test: "vtr_reg_strong", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "", cmake: "-DVTR_ASSERT_LEVEL=3 -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_strong_odin", cores: "16", options: "-skip_qor", cmake: "-DVTR_ASSERT_LEVEL=3 -DVTR_ENABLE_SANITIZE=ON -DWITH_ODIN=ON", extra_pkgs: "libeigen3-dev"}
- {test: "vtr_reg_system_verilog", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}
- {test: "odin_reg_strong", cores: "16", options: "", cmake: "-DWITH_ODIN=ON", extra_pkgs: ""}
- {test: "parmys_reg_strong", cores: "16", options: "", cmake: "-DYOSYS_F4PGA_PLUGINS=ON", extra_pkgs: ""}

env:
DEBIAN_FRONTEND: "noninteractive"

steps:

# TODO: This runnner is running on a self-hosted CPU. In order to upgrade
# to v4, need to upgrade the machine to support node20.
- uses: actions/checkout@v3
with:
submodules: 'true'

- name: Setup
run: stdbuf -i0 -i0 -e0 ./.github/scripts/hostsetup.sh

- name: Install external libraries
run: apt install -y ${{ matrix.extra_pkgs }}
if: ${{ matrix.extra_pkgs }}

- name: Execute test script
run: stdbuf -i0 -o0 -e0 ./.github/scripts/run-vtr.sh
env:
VPR_NUM_WORKERS: 4
VTR_TEST: ${{ matrix.test }}
VTR_TEST_OPTIONS: ${{ matrix.options }}
VTR_CMAKE_PARAMS: ${{ matrix.cmake }}
NUM_CORES: ${{ matrix.cores }}

- name: Upload test results
# If the job was not cancelled, we want to save the result (this includes
# when the job fails). See warning here:
# https://docs.github.com/en/actions/learn-github-actions/expressions#always
if: ${{ !cancelled() }}
# TODO: This runnner is running on a self-hosted CPU. In order to upgrade
# to v4, need to upgrade the machine to support node20.
uses: actions/upload-artifact@v3
with:
name: ${{matrix.test}}_test_results
path: |
**/results*.gz
**/plot_*.svg
**/qor_results*.tar.gz
Build:
name: 'B: Building VtR'
runs-on: ubuntu-22.04
Expand Down
2 changes: 1 addition & 1 deletion BUILDING.md
Original file line number Diff line number Diff line change
Expand Up @@ -46,7 +46,7 @@ If you download a different version of those tools, then those versions may not

To verfiy that VTR has been installed correctly run::

./vtr_flow/scripts/run_vtr_task.py regression_tests/vtr_reg_basic/basic_timing
./vtr_flow/scripts/run_vtr_task.py ./vtr_flow/tasks/regression_tests/vtr_reg_basic/basic_timing

The expected output is::

Expand Down
10 changes: 10 additions & 0 deletions doc/src/api/vpr/grid.rst
Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
========
Grid
========

DeviceGrid
-------

.. doxygenclass:: DeviceGrid
:project: vpr
:members:
1 change: 1 addition & 0 deletions doc/src/api/vpr/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@ VPR API
:maxdepth: 1

contexts
grid
mapping
netlist
route_tree
Expand Down
6 changes: 6 additions & 0 deletions doc/src/api/vpr/rr_graph.rst
Original file line number Diff line number Diff line change
Expand Up @@ -35,3 +35,9 @@ RRSpatialLookup
:project: librrgraph
:members:

rr_graph_utils
---------------

.. doxygenfile:: rr_graph_utils.h
:project: librrgraph
:sections: briefdescription detaileddescription func prototype user-defined public-func
35 changes: 35 additions & 0 deletions doc/src/api/vprinternals/router_lookahead.rst
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
==============
Router Lookahead
==============

e_router_lookahead
----------
.. doxygenenum:: e_router_lookahead
:project: vpr


RouterLookahead
----------
.. doxygenclass:: RouterLookahead
:project: vpr
:members:

MapLookahead
----------
.. doxygenclass:: MapLookahead
:project: vpr

make_router_lookahead
----------
.. doxygenfunction:: make_router_lookahead
:project: vpr

get_cached_router_lookahead
----------
.. doxygenfunction:: get_cached_router_lookahead
:project: vpr

invalidate_router_lookahead_cache
----------
.. doxygenfunction:: invalidate_router_lookahead_cache
:project: vpr
3 changes: 2 additions & 1 deletion doc/src/api/vprinternals/vpr_router.rst
Original file line number Diff line number Diff line change
Expand Up @@ -7,4 +7,5 @@ VPR Router
.. toctree::
:maxdepth: 1

router_heap
router_heap
router_lookahead
9 changes: 9 additions & 0 deletions doc/src/vpr/command_line_usage.rst
Original file line number Diff line number Diff line change
Expand Up @@ -1306,6 +1306,15 @@ The following options are only valid when the router is in timing-driven mode (t

**Default:** ``1.2``

.. option:: --astar_offset <float>

Sets how aggressive the directed search used by the timing-driven router is.
It is a subtractive adjustment to the lookahead heuristic.

Values between 0 and 1e-9 are resonable; higher values may increase quality at the expense of run-time.

**Default:** ``0.0``

.. option:: --router_profiler_astar_fac <float>

Controls the directedness of the timing-driven router's exploration when doing router delay profiling of an architecture.
Expand Down
13 changes: 13 additions & 0 deletions libs/libarchfpga/src/device_grid.h
Original file line number Diff line number Diff line change
Expand Up @@ -6,6 +6,7 @@
#include <cmath>
#include "vtr_ndmatrix.h"
#include "physical_types.h"
#include "vtr_geometry.h"

/**
* @brief s_grid_tile is the minimum tile of the fpga
Expand Down Expand Up @@ -73,6 +74,18 @@ class DeviceGrid {
return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].height_offset;
}

///@brief Returns a rectangle which represents the bounding box of the tile at the given location.
inline vtr::Rect<int> get_tile_bb(const t_physical_tile_loc& tile_loc) const {
t_physical_tile_type_ptr tile_type = get_physical_type(tile_loc);

int tile_xlow = tile_loc.x - get_width_offset(tile_loc);
int tile_ylow = tile_loc.y - get_height_offset(tile_loc);
int tile_xhigh = tile_xlow + tile_type->width - 1;
int tile_yhigh = tile_ylow + tile_type->height - 1;

return {{tile_xlow, tile_ylow}, {tile_xhigh, tile_yhigh}};
}

///@brief Return the metadata of the tile at the specified location
inline const t_metadata_dict* get_metadata(const t_physical_tile_loc& tile_loc) const {
return grid_[tile_loc.layer_num][tile_loc.x][tile_loc.y].meta;
Expand Down
14 changes: 10 additions & 4 deletions libs/libarchfpga/src/physical_types.h
Original file line number Diff line number Diff line change
Expand Up @@ -925,10 +925,10 @@ struct t_logical_block_type {
std::vector<t_physical_tile_type_ptr> equivalent_tiles; ///>List of physical tiles at which one could
///>place this type of netlist block.

std::unordered_map<int, t_pb_graph_pin*> pin_logical_num_to_pb_pin_mapping; /* pin_logical_num_to_pb_pin_mapping[pin logical number] -> pb_graph_pin ptr} */
std::unordered_map<const t_pb_graph_pin*, int> primitive_pb_pin_to_logical_class_num_mapping; /* primitive_pb_pin_to_logical_class_num_mapping[pb_graph_pin ptr] -> class logical number */
std::vector<t_class> primitive_logical_class_inf; /* primitive_logical_class_inf[class_logical_number] -> class */
std::unordered_map<const t_pb_graph_node*, t_class_range> pb_graph_node_class_range;
std::unordered_map<int, t_pb_graph_pin*> pin_logical_num_to_pb_pin_mapping; /* pin_logical_num_to_pb_pin_mapping[pin logical number] -> pb_graph_pin ptr} */
std::unordered_map<const t_pb_graph_pin*, int> primitive_pb_pin_to_logical_class_num_mapping; /* primitive_pb_pin_to_logical_class_num_mapping[pb_graph_pin ptr] -> class logical number */
std::vector<t_class> primitive_logical_class_inf; /* primitive_logical_class_inf[class_logical_number] -> class */
std::unordered_map<const t_pb_graph_node*, t_class_range> primitive_pb_graph_node_class_range; /* primitive_pb_graph_node_class_range[primitive_pb_graph_node ptr] -> class range for that primitive*/

// Is this t_logical_block_type empty?
bool is_empty() const;
Expand Down Expand Up @@ -1240,6 +1240,12 @@ class t_pb_graph_node {

int placement_index;

/*
* There is a root-level pb_graph_node assigned to each logical type. Each logical type can contain multiple primitives.
* If this pb_graph_node is associated with a primitive, a unique number is assigned to it within the logical block level.
*/
int primitive_num = OPEN;

/* Contains a collection of mode indices that cannot be used as they produce conflicts during VPR packing stage
*
* Illegal modes do arise when children of a graph_node do have inconsistent `edge_modes` with respect to
Expand Down
2 changes: 1 addition & 1 deletion libs/libarchfpga/src/physical_types_util.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -965,7 +965,7 @@ t_class_range get_pb_graph_node_class_physical_range(t_physical_tile_type_ptr /*
const t_pb_graph_node* pb_graph_node) {
VTR_ASSERT(pb_graph_node->is_primitive());

t_class_range class_range = logical_block->pb_graph_node_class_range.at(pb_graph_node);
t_class_range class_range = logical_block->primitive_pb_graph_node_class_range.at(pb_graph_node);
int logical_block_class_offset = sub_tile->primitive_class_range[sub_tile_relative_cap].at(logical_block).low;

class_range.low += logical_block_class_offset;
Expand Down
16 changes: 15 additions & 1 deletion libs/librrgraph/src/base/check_rr_graph.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,7 @@
#include "physical_types_util.h"

#include "describe_rr_node.h"
#include "rr_graph_utils.h"

/*********************** Subroutines local to this module *******************/

Expand Down Expand Up @@ -389,16 +390,29 @@ void check_rr_node(const RRGraphView& rr_graph,

switch (rr_type) {
case SOURCE:
case SINK:
if (type == nullptr) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow);
}

if (xlow != (xhigh - type->width + 1) || ylow != (yhigh - type->height + 1)) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d)\n", inode, rr_type, xlow, ylow, xhigh, yhigh);
}
break;
case SINK: {
if (type == nullptr) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) is at an illegal clb location (%d, %d).\n", inode, rr_type, xlow, ylow);
}

vtr::Rect<int> tile_bb = grid.get_tile_bb({xlow, ylow, layer_num});
if (xlow < tile_bb.xmin() || ylow < tile_bb.ymin() || xhigh > tile_bb.xmax() || yhigh > tile_bb.ymax()) {
VPR_FATAL_ERROR(VPR_ERROR_ROUTE,
"in check_rr_node: node %d (type %d) has endpoints (%d,%d) and (%d,%d), which is outside the bounds of the grid tile containing it.\n", inode, rr_type, xlow, ylow, xhigh, yhigh);
}
break;
}
case IPIN:
case OPIN:
if (type == nullptr) {
Expand Down
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