Merge pull request #2498 from byuccl/channel_fix

Fix division by zero on arches with many different channel widths
verilog-to-routing · Mar 7, 2024 · bc24720 · bc24720
2 parents e5af061 + eddf287
commit bc24720
Showing 1 changed file with 5 additions and 0 deletions.
diff --git a/vpr/src/route/rr_graph.cpp b/vpr/src/route/rr_graph.cpp
@@ -3723,6 +3723,11 @@ static void load_uniform_connection_block_pattern(vtr::NdMatrix<int, 6>& tracks_
         /* Bi-directional treats each track separately, uni-directional works with pairs of tracks */
         for (int j = 0; j < (Fc / group_size); ++j) {
             int max_chan_width = (((side == TOP) || (side == BOTTOM)) ? x_chan_width : y_chan_width);
+
+            // if the number of tracks we can assign is zero break from the loop
+            if (max_chan_width == 0) {
+                break;
+            }
             float step_size = (float)max_chan_width / (float)(Fc * num_phys_pins);
 
             VTR_ASSERT(Fc > 0);