[core] debug

verilog-to-routing · Jul 5, 2024 · c71c3b9 · c71c3b9
1 parent 4da28ff
commit c71c3b9
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -868,7 +868,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
                 break;
             case RIGHT:
                 /* Consider the routing channel that is connected to the top side of the switch block */
-                chan_side = TOP;
+                chan_side = BOTTOM;
                 /* The input pins of the routing channel come from the left side of Grid[x+1][y+1] */
                 ix = rr_gsb.get_sb_x() + 1;
                 iy = rr_gsb.get_sb_y();
@@ -884,7 +884,7 @@ RRGSB build_one_tileable_rr_gsb(const DeviceGrid& grids,
                 break;
             case LEFT:
                 /* Consider the routing channel that is connected to the top side of the switch block */
-                chan_side = TOP;
+                chan_side = BOTTOM;
                 /* The input pins of the routing channel come from the right side of Grid[x][y+1] */
                 ix = rr_gsb.get_sb_x();
                 iy = rr_gsb.get_sb_y();