pass_requirements update

verilog-to-routing · Aug 5, 2024 · c7d3487 · c7d3487
1 parent 7fc2332
commit c7d3487
Show file tree

Hide file tree

Showing 2 changed files with 5 additions and 2 deletions.
diff --git a/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_pack_place.txt b/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_pack_place.txt
@@ -19,5 +19,6 @@ device_limiting_resources;Equal()
 device_name;Equal()
 
 #Run-time
-pack_time;RangeAbs(0.10,10.0,2)
+#pack_time;RangeAbs(0.10,10.0,2) -> Yosys32 compatible 
+pack_time;RangeAbs(0.08,10.0,2)
 place_time;RangeAbs(0.10,10.0,2)
diff --git a/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt b/vtr_flow/parse/pass_requirements/common/pass_requirements.vpr_route_min_chan_width_small.txt
@@ -11,7 +11,9 @@ min_chan_width_routing_area_total;Range(0.5,1.6)
 min_chan_width_routing_area_per_tile;Range(0.5,1.6)
 
 #Run-time metrics
-min_chan_width_route_time;RangeAbs(0.10,15.0,2)
+#min_chan_width_route_time;RangeAbs(0.10,15.0,2) -> Yosys32 compatible 
+min_chan_width_route_time;RangeAbs(0.09,15.0,2)
+
 
 #Peak memory
 #We set a 100MiB minimum threshold since the memory