[core] debugging

verilog-to-routing · Jul 8, 2024 · ddc3ac4 · ddc3ac4
1 parent 5ca82e5
commit ddc3ac4
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_edge_builder.cpp
@@ -144,9 +144,7 @@ void build_rr_graph_edges(const RRGraphView& rr_graph,
 
             /* adapt the opin_to_track_map for the GSB nodes */
             t_pin2track_map opin2track_map; /* [0..gsb_side][0..num_opin_node][track_indices] */
-            if (ix < gsb_range.x() && iy < gsb_range.y()) {
-                opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides);
-            }
+            opin2track_map = build_gsb_opin_to_track_map(rr_graph, rr_gsb, grids, segment_inf, Fc_out, opin2all_sides);
 
             /* adapt the switch_block_conn for the GSB nodes */
             t_track2track_map sb_conn; /* [0..from_gsb_side][0..chan_width-1][track_indices] */

diff --git a/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/tileable_rr_graph/tileable_rr_graph_gsb.cpp
@@ -1318,6 +1318,9 @@ t_pin2track_map build_gsb_opin_to_track_map(const RRGraphView& rr_graph,
                     continue;
                 }
             }
+            if (rr_gsb.get_sb_x() == grids.width() - 1 || rr_gsb.get_sb_y() == grids.height() - 1) {
+                skip_conn2track = true;
+            }
 
             if (true == skip_conn2track) {
                 continue;