[WIP] Upgrade to yosys 0.29 #2303
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yosys: Adding yosys/ as an external git subtree from https://github.com/YosysHQ/yosys.git yosys-0.28
git-subtree-dir: yosys git-subtree-split: 0d6f4b068338c25f3de4ddab0747f714602037b5
yosys: Updating yosys/ (external git subtree from https://github.com/YosysHQ/yosys.git yosys-0.29)
9c5a60eb20 Release version 0.29 0469405abf Bump version 266036c6f9 Merge pull request #3756 from YosysHQ/krys/sim_writeback 0aeb6105eb Merge pull request #3736 from jix/conc_assertion_in_unclocked_proc_ctx ec56e625f4 Merge pull request #3742 from jix/fix_rename_witness_cell_renames 5a4e72f57a Fix sim writeback check for yw_cosim 4251d37f4f Merge pull request #3610 from YosysHQ/synthprop f93671eb85 Bump version 32f5fca2aa Merge pull request #3694 from daglem/struct-attributes fb7f3bb290 Cleaner tests for RTLIL cells in struct_dynamic_range.sv ad437c178d Handling of attributes for struct / union variables 7bff8b63b3 rename: Fix renaming cells in -witness mode cee3cb31b9 Merge pull request #3734 from jix/fix_unbased_unsized_const 51dd029024 Bump version 8611429237 ABC9: Cell Port Bug Patch (#3670) 3cbca5064c verific: Handle non-seq properties with VerificClocking conditions ec47bf1745 verific: Handle conditions when using sva_at_only in VerificClocking 985f4926b7 verilog: Fix const eval of unbased unsized constants 7efc50367e Bump version 88ae463ffe Merge pull request #3732 from hzeller/20230417-remote-statement-no-effect a3a8f7be38 Remove a statement without effect. a9c792dcee Bump version d0855576ae Next dev cycle 550a5b7b6b Update license 713b7d3e26 added support for latched output reset 131b557727 Initial implementation of synthesizable assertions git-subtree-dir: yosys git-subtree-split: 9c5a60eb20104f7c320e263631c1371af9576911
f7a8284c7b Release version 0.30
73badeccef Bump version
8cb3bab479 Merge pull request #3792 from pu-cc/gatemate-bram-updates
61387d78b7 gatemate: Prevent implicit declaration of `ram_{we,en}`
62fc118548 Merge pull request #3790 from zeldin/makefile-posix-test
7c606bd5a3 Merge pull request #3791 from nakengelhardt/nak/show_attr_wires
6f5d984bdb Merge pull request #3778 from jix/yw_clk2fflogic
88c849d112 Bump version
d7f25165a5 Add ninitff line to aiger .aim files
0707b911c7 show: add -viewer none option
4b986c9c65 fix wire color after BUF
2004a9ff4a gatemate: Add CC_FIFO_40K simulation model
c244a7161b gatemate: Fix SDP read behavior
43b807fe6f Bump version
1cd1e57e3c Fix use of non-POSIX test expressions in Makefile
fb7af093a8 intel_alm: re-enable 8x40-bit M10K support
26555a998d show -colorattr: extend colors to arrows when wires have attribute
8596c5ce49 Bump version
cac1bc6fbe intel_alm: enable M10K initialisation
ec8d7b1c68 abc9_ops -prep_hier to unmap entire module
862631d657 Add ABC9 DSP cascade test
00b0e850db intel_alm: re-enable carry chains for ABC9
e36c71b5b7 Use clk2fflogic attr on cells to track original FF names in witnesses
7caeb922a0 sim: Run level triggered async updates to fixpoint during initialization
52c8c28d2c Add recover_names pass to recover names post-mapping
57c9eb70fe Bump version
5e36effe3c Merge pull request #3777 from YosysHQ/micko/vhdl_verific
ecd289c100 Fix importing parametrized VHDL entity
4f3d1be96a Merge pull request #3767 from YosysHQ/krys/yw_fix
5fb1223861 Merge pull request #3733 from AdamHillier/aiger-inputs
890849447f Merge pull request #3716 from antmicro/kr/brackets
cdeef5481c Bump version
e7156c644d Standard compliance for tests/verilog/block_labels.ys
ad2b04d63a sim: Fix cosimulation with nested modules having unconnected inputs
e6f3914800 smt2: Use smt bv offset for `$any*`'s smtoffset
147cceb516 Bump version
52ad7a47f3 Assign wires an smtoffset
c2285b3460 fix file rights
07e76fcaca Merge pull request #3751 from RTLWorks/main/issue2525
693c609eec Merge branch 'YosysHQ:master' into main/issue2525
665e0f6131 remove new line per maintainer request
acfdc5cc42 Merge pull request #3755 from RTLWorks/muthu/issue3498
6b3e6d96a3 Fix missing brackets around else
d82bae32be Bump version
c855502bd5 Update passes/techmap/libparse.cc
7aab324e85 Merge pull request #3737 from yrabbit/all-primitives-script
5c7cc6ff06 Merge pull request #3745 from rfuest/gowin_alu
226a224640 Merge pull request #3749 from lethalbit/aki/plugin-stuff
f790e00478 Next dev cycle
17cfc969dd [YOSYS] Issue #3498 - Fix Synopsys style unquoted Liberty style function body parsing with unittest
8341fd450e Merge branch 'master' into all-primitives-script
d2f3251528 adding unittest
81e089cb60 [YOSYS-2525] fix read_liberty newline handling verilog-to-routing#2525 - newlines can be allowed in function parsing
4f6a66e257 Merge branch 'master' into all-primitives-script
bb240665b7 plugin: shuffled the `#ifdef WITH_PYTHON`'s around to un-tangle the code and pulled out the check for the `.py` extension so it will complain if you try to load a python extension without python support
572c8df9a8 plugin: Re-vamped how plugin lookup was done to make it more consistent with the rest of yosys, and prevented a case where you could end up with `.so.so` on the end
30f1d10948 gowin: Fix X output of $alu techmap
2bab787729 Merge branch 'master' into all-primitives-script
a1dd794ff8 gowin: Add all the primitives.
3861cc31f0 Add outputs before inputs to the sigmap in the AIGER backend.
git-subtree-dir: yosys
git-subtree-split: f7a8284c7b095bca4bc2c65032144c4e3264ee4d
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Moving forward with yosys-0.30 in #2336 PR. |
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