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[LOGGING] Fixed LUT Sizing Issue #2686

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AlexandreSinger
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@AlexandreSinger AlexandreSinger commented Aug 14, 2024

Fixed issue where the LUT sizing for printing the circuit statistics was using the port width instead of the number of input pins.

The CLMA example from the issue:
image
Now looks like this:
image

Which makes a lot more sense.

closes #2685

EDIT:

Based on Vaughn's comments below, changed the format of the statistics to the following:
image

This now includes the total number of LUTs (called .names here), as well as a breakdown of their sizes.

@github-actions github-actions bot added VPR VPR FPGA Placement & Routing Tool lang-cpp C/C++ code labels Aug 14, 2024
@AlexandreSinger
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I am suprised this change failed CI. Looks like the parsing scripts may have been relying on this bug to count the number of LUTs:
image

I think these scripts may need to be checked. Or maybe it is as simple as updating the golden results.

@vaughnbetz
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Thanks. I suggest adding a total LUTs line as well, and then updating the parsing rule. That should fix CI (seems we were parsing the 6-LUT line as the total LUTs! ).

@AlexandreSinger
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AlexandreSinger commented Aug 15, 2024

@vaughnbetz That makes sense to me! Would you like me to include 0-LUTs in that total? I am not 100% on the semantics of what a "0-LUT" is beyond being a constant generator.

@vaughnbetz
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Sure, I'd count it. It is a constant generator.

@AlexandreSinger AlexandreSinger force-pushed the feature-lut-size-logging branch from 3d6fc1c to d2d4254 Compare August 16, 2024 00:18
@AlexandreSinger
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@vaughnbetz I have updated the circuit statistics to include the total number of LUTs. I have tried to follow the format of the rest of the logs:
image

Let me know what you think. I personally like it; but I can understand if people may be confused by ".output" coming after all the LUT sizes.

@vaughnbetz
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Looks good to me!

@AlexandreSinger AlexandreSinger force-pushed the feature-lut-size-logging branch from d2d4254 to e72dccf Compare August 16, 2024 17:38
The size of the LUTs were being calculated incorrectly by using the width
of the port instead of the actual number of pins in the port.

The parsing scripts for the golden results were also incorrect since
they were using the number of 6-LUTs as the total number of LUTs.
@AlexandreSinger AlexandreSinger force-pushed the feature-lut-size-logging branch from e72dccf to 859276c Compare August 16, 2024 21:40
@AlexandreSinger
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@vaughnbetz This PR has passed CI. Please review and merge when you have a moment. I have updated the parsing script, which required me to regenerate the golden results (since some testcases were mis-counting the number of LUTs in designs).

@vaughnbetz vaughnbetz merged commit 67e5558 into verilog-to-routing:master Aug 20, 2024
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[Logging] Incorrect LUT Sizes Circuit Statistic Printing
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