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Add flat version of sync_netlists_to_routing #2691
Add flat version of sync_netlists_to_routing #2691
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Needs to be tested with stratix iv arch. |
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Looks nice overall. Good mapping reverse engineering!
Themes:
- Add Doxygen comments in various spots.
- Add warnings / asserts / comments on clocks needing to be ideal, and minimize the amount of code that checks if something is a clock. Please file an issue on clock remapping with flat routing. It may not be that hard to add clock support. In many cases there won't be any pin swappability, and when there is due to a small intra-cluster crossbar I think the code to figure out the pins is basically the same.
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The even/odd NoC routing failure is a known one that Soheil is working on; ignore it (he will disable the test if needed). (unit tests) |
Hang also found a vulnerability / error in the connection router destructor with parallel routing and has fixed it in another PR. Probably not related but it would be good to rebase once that change goes in. |
todo: add flat spree.v to basic and run with sanitizer & valgrind |
Closing this PR and re-opening from a branch in this repo... since the CI doesn't seem to pull the right version? |
…-routing Add flat version of sync_netlists_to_routing (see #2691)
Run flat changes the internal cluster routing, and can also rotate truth tables in LUTs. To generate a bitstream or perform post-routing simulation, we need to update the intra-cluster routing data and mapping data of what inputs/outputs have been re-ordered by the router. this PR does that.
Description
Made a sync_netlists_to_routing flat routine which rebuilds the clustered netlist and the intra-cluster routing (pb_routes) and updates the atom lookup data structure.
Related Issue
Issue from OpenFPGA repo:
Motivation and Context
Flat routing won't be usable by QuickLogic, OpenFPGA etc. without this change.
How Has This Been Tested?
TODO:
Types of changes
Checklist: