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Inverse of the average number of tracks per channel #2741

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4a5c1c9
add ChanPlaceCostFacContainer
soheilshahrouz Sep 22, 2024
e793e21
remove std::max calls
soheilshahrouz Sep 22, 2024
8ef4144
remove std::min calls
soheilshahrouz Sep 22, 2024
6d870c4
remove dead code
soheilshahrouz Sep 22, 2024
1106c75
move part of chanx_place_cost_fac_ initialization to the loop by chan…
soheilshahrouz Sep 22, 2024
c9af1fb
compute inverse average channel for all valid indices
soheilshahrouz Sep 22, 2024
35a7e3e
inline operator()
soheilshahrouz Sep 23, 2024
0693f1d
add comments
soheilshahrouz Sep 23, 2024
625a610
update basic golder results
soheilshahrouz Sep 23, 2024
08d152c
increase channel width for two run failures in vtr_strong amd vtr_st…
soheilshahrouz Sep 23, 2024
9148e08
Merge branch 'master' into temp_chanx_place_cost_fac
soheilshahrouz Sep 24, 2024
afe22e2
update golden results in strong and strong_odin
soheilshahrouz Sep 24, 2024
451b929
use integer indices in vtr::NdOffsetMatrix to enable using negative i…
soheilshahrouz Sep 24, 2024
099d040
replace ChanPlaceCostFacContainer with vtr::NdOffsetMatrix
soheilshahrouz Sep 24, 2024
888ac89
vtr::NdOffsetMatrix range is not inclusive
soheilshahrouz Sep 24, 2024
6f5a3aa
fix compilation warnings
soheilshahrouz Sep 24, 2024
d4e1715
Merge branch 'master' into temp_chanx_place_cost_fac
vaughnbetz Sep 26, 2024
56b989a
initialize chany_place_cost_fac_
soheilshahrouz Sep 28, 2024
b7561cc
Merge branch 'master' into temp_chanx_place_cost_fac
soheilshahrouz Oct 1, 2024
566880e
Merge branch 'master' into temp_chanx_place_cost_fac
soheilshahrouz Oct 3, 2024
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185 changes: 63 additions & 122 deletions vpr/src/place/net_cost_handler.cpp

Large diffs are not rendered by default.

42 changes: 38 additions & 4 deletions vpr/src/place/net_cost_handler.h
Original file line number Diff line number Diff line change
Expand Up @@ -190,17 +190,45 @@ class NetCostHandler {
vtr::vector<ClusterNetId, double> proposed_net_cost_;
vtr::vector<ClusterNetId, NetUpdateState> bb_update_status_;

/**
* @brief This class is used to store the inverse of average channel
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* width between two channels inclusive. The difference of this class
* with vtr::NdMatrix<float, 2> is that its index spaces starts from -1.
* When the inverse average channel width is factored in, the channel
* immediately below and the channel immediately to the left of the
* bounding box are also considered. This class makes sure that when
* the left and bottom edges of the bounding boxes are moved by one unit,
* the indices used to access inverse average channel width are still valid.
*/
class ChanPlaceCostFacContainer : public vtr::NdMatrix<float, 2> {
public:
/**
* @brief Returns the inverse average channel width between channels low
* and high inclusive.
* @param high The high channel number.
* @param low The low channel number.
* @return The inverse average channel width between the given channel
* numbers.
*/
inline float& operator()(int high, int low) {
return this->operator[]((size_t)(high + 1)).operator[]((size_t)(low + 1));
}

private:
using vtr::NdMatrix<float, 2>::operator[];
};

/**
* @brief Matrices below are used to precompute the inverse of the average
* number of tracks per channel between [subhigh] and [sublow]. Access
* them as chan?_place_cost_fac[subhigh][sublow]. They are used to
* them as chan?_place_cost_fac(subhigh, sublow). They are used to
* speed up the computation of the cost function that takes the length
* of the net bounding box in each dimension, divided by the average
* number of tracks in that direction; for other cost functions they
* will never be used.
*/
vtr::NdMatrix<float, 2> chanx_place_cost_fac_; // [0...device_ctx.grid.width()-2]
vtr::NdMatrix<float, 2> chany_place_cost_fac_; // [0...device_ctx.grid.height()-2]
ChanPlaceCostFacContainer chanx_place_cost_fac_; // [-1...device_ctx.grid.width()-1]
ChanPlaceCostFacContainer chany_place_cost_fac_; // [-1...device_ctx.grid.height()-1]


private:
Expand Down Expand Up @@ -243,6 +271,13 @@ class NetCostHandler {
/**
* @brief Allocates and loads the chanx_place_cost_fac and chany_place_cost_fac arrays with the inverse of
* the average number of tracks per channel between [subhigh] and [sublow].
*
* @details This is only useful for the cost function that takes the length of the net bounding box in each
* dimension divided by the average number of tracks in that direction. For other cost functions, you don't
* have to bother calling this routine; when using the cost function described above, however, you must always
* call this routine before you do any placement cost determination. The place_cost_exp factor specifies to
* what power the width of the channel should be taken -- larger numbers make narrower channels more expensive.
*
* @param place_cost_exp It is an exponent to which you take the average inverse channel capacity;
* a higher value would favour wider channels more over narrower channels during placement (usually we use 1).
*/
Expand Down Expand Up @@ -383,7 +418,6 @@ class NetCostHandler {
* @param old_edge_coord The current known bounding box of the net
* @param new_num_block_on_edge The new bb calculated by this function
* @param new_edge_coord The new bb edge calculated by this function
*
*/
inline void update_bb_edge_(ClusterNetId net_id,
std::vector<t_2D_bb>& bb_edge_new,
Expand Down
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 2.61 vpr 61.47 MiB -1 -1 0.41 18112 3 0.09 -1 -1 33112 -1 -1 69 99 1 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 62948 99 130 353 483 1 220 299 13 13 169 clb auto 22.6 MiB 0.04 540 29270 3582 8022 17666 61.5 MiB 0.02 0.00 36 1178 8 3.33e+06 2.19e+06 481319. 2848.04 0.89
k4_N10_memSize16384_memData64.xml diffeq1.v common 4.95 vpr 64.53 MiB -1 -1 0.72 23016 23 0.29 -1 -1 34312 -1 -1 71 162 0 5 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 66076 162 96 1200 1141 1 688 334 13 13 169 clb auto 25.7 MiB 0.17 4622 86026 24278 56070 5678 64.5 MiB 0.16 0.00 50 10124 42 3.33e+06 2.58e+06 641417. 3795.37 1.79
k4_N10_memSize16384_memData64.xml single_wire.v common 1.00 vpr 58.46 MiB -1 -1 0.15 16036 1 0.02 -1 -1 29872 -1 -1 0 1 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 59864 1 1 1 2 0 1 2 3 3 9 -1 auto 20.0 MiB 0.00 2 3 3 0 0 58.5 MiB 0.00 0.00 2 2 1 30000 0 1489.46 165.495 0.00
k4_N10_memSize16384_memData64.xml single_ff.v common 1.02 vpr 58.49 MiB -1 -1 0.16 16284 1 0.02 -1 -1 29928 -1 -1 1 2 0 0 success v8.0.0-11333-g6a44da44e release IPO VTR_ASSERT_LEVEL=2 GNU 9.4.0 on Linux-4.15.0-213-generic x86_64 2024-09-18T20:37:10 betzgrp-wintermute.eecg.utoronto.ca /home/singera8/vtr-verilog-to-routing/vtr_flow/tasks 59892 2 1 3 4 1 3 4 3 3 9 -1 auto 19.7 MiB 0.00 4 9 6 0 3 58.5 MiB 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.91 vpr 65.59 MiB -1 -1 0.21 21296 3 0.05 -1 -1 39652 -1 -1 69 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67160 99 130 353 483 1 220 299 13 13 169 clb auto 26.9 MiB 0.03 692 29270 3600 8725 16945 65.6 MiB 0.03 0.00 30 1400 11 3.33e+06 2.19e+06 408126. 2414.95 1.08
k4_N10_memSize16384_memData64.xml diffeq1.v common 4.43 vpr 69.27 MiB -1 -1 0.31 26352 23 0.22 -1 -1 41100 -1 -1 71 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70936 162 96 1200 1141 1 688 334 13 13 169 clb auto 30.2 MiB 0.11 5199 75604 21039 49822 4743 69.3 MiB 0.10 0.00 54 10333 34 3.33e+06 2.58e+06 696024. 4118.48 2.85
k4_N10_memSize16384_memData64.xml single_wire.v common 0.25 vpr 63.52 MiB -1 -1 0.05 19840 1 0.01 -1 -1 35512 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65048 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.5 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
k4_N10_memSize16384_memData64.xml single_ff.v common 0.26 vpr 63.64 MiB -1 -1 0.06 19968 1 0.01 -1 -1 35756 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=4 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:34:43 fv-az841-217 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 65172 2 1 3 4 1 3 4 3 3 9 -1 auto 25.2 MiB 0.00 6 9 4 1 4 63.6 MiB 0.00 0.00 18 13 1 30000 30000 3112.78 345.864 0.01
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
arch circuit script_params vtr_flow_elapsed_time error odin_synth_time max_odin_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_time placed_wirelength_est place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.83 0.03 8960 4 0.21 -1 -1 36092 -1 -1 72 99 1 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 34468 99 130 378 508 1 260 302 13 13 169 clb auto 0.05 602 0.16 0.00 36 1421 8 3.33e+06 2.28e+06 481319. 2848.04 0.73
k4_N10_memSize16384_memData64.xml diffeq1.v common 2.98 0.04 8784 23 0.24 -1 -1 34032 -1 -1 72 162 0 5 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 37256 162 96 1214 1147 1 676 335 13 13 169 clb auto 0.14 4543 0.24 0.00 50 10225 50 3.33e+06 2.61e+06 641417. 3795.37 1.46
k4_N10_memSize16384_memData64.xml single_wire.v common 0.28 0.01 5576 1 0.01 -1 -1 29552 -1 -1 0 1 0 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 22644 1 1 1 2 0 1 2 3 3 9 -1 auto 0.00 2 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
k4_N10_memSize16384_memData64.xml single_ff.v common 0.33 0.01 5472 1 0.01 -1 -1 29636 -1 -1 1 2 0 0 success v8.0.0-2985-gac43b6bd1-dirty release IPO VTR_ASSERT_LEVEL=2 GNU 7.5.0 on Linux-4.15.0-60-generic x86_64 2020-11-03T08:54:06 betzgrp-wintermute.eecg.utoronto.ca /home/elgamma8/research/gold/vtr-verilog-to-routing 22508 2 1 3 4 1 3 4 3 3 9 -1 auto 0.00 4 0.00 0.00 16 5 1 30000 30000 2550.78 283.420 0.01
arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time
k4_N10_memSize16384_memData64.xml ch_intrinsics.v common 1.31 vpr 65.73 MiB 0.02 9472 -1 -1 4 0.19 -1 -1 42360 -1 -1 72 99 1 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 67304 99 130 378 508 1 260 302 13 13 169 clb auto 27.0 MiB 0.03 975 80250 22205 36468 21577 65.7 MiB 0.08 0.00 36 1771 10 3.33e+06 2.28e+06 481319. 2848.04 0.42
k4_N10_memSize16384_memData64.xml diffeq1.v common 3.61 vpr 69.33 MiB 0.02 9472 -1 -1 23 0.20 -1 -1 41432 -1 -1 72 162 0 5 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 70992 162 96 1214 1147 1 676 335 13 13 169 clb auto 30.4 MiB 0.12 4968 89886 25356 58643 5887 69.3 MiB 0.12 0.00 52 9486 14 3.33e+06 2.61e+06 671819. 3975.26 2.33
k4_N10_memSize16384_memData64.xml single_wire.v common 0.21 vpr 63.40 MiB 0.01 5888 -1 -1 1 0.01 -1 -1 35384 -1 -1 0 1 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64920 1 1 1 2 0 1 2 3 3 9 -1 auto 25.1 MiB 0.00 2 3 1 2 0 63.4 MiB 0.00 0.00 2 1 1 30000 0 1489.46 165.495 0.00
k4_N10_memSize16384_memData64.xml single_ff.v common 0.20 vpr 63.39 MiB 0.01 5760 -1 -1 1 0.01 -1 -1 33768 -1 -1 1 2 0 0 success d41921e Release IPO VTR_ASSERT_LEVEL=3 GNU 11.4.0 on Linux-6.8.0-1014-azure x86_64 2024-09-23T16:25:31 fv-az1536-937 /home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing 64916 2 1 3 4 1 3 4 3 3 9 -1 auto 25.1 MiB 0.00 6 9 4 1 4 63.4 MiB 0.00 0.00 18 13 1 30000 30000 3112.78 345.864 0.01
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