peepopt: continue tests

tests/various/peepopt_muldiv_c.ys

@@ -1,4 +1,4 @@
-# basic pattern: (a * b) / c
+# Basic pattern transformed: (a * b) / c
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
@@ -15,14 +15,66 @@ select -assert-count 1 t:$mul
 select -assert-count 0 t:$div
 design -reset
 
+# Transformed on symmetry in multiplication
+# read_verilog <<EOT
+# module top(
+# 	input signed [3:0] a,
+# 	output signed [7:0] y,
+# );
+#     wire signed [7:0] mul;
+# 	assign mul = 4'sd6 * a;
+# 	assign y = mul / 8'sd3;
+# endmodule
+# EOT
+# equiv_opt -assert peepopt
+# design -load postopt
+# select -assert-count 1 t:$mul
+# select -assert-count 0 t:$div
+# design -reset
+
+# Transformed on b == c
 read_verilog <<EOT
 module top(
-	input [3:0] a,
-	output [7:0] y,
+	input signed [3:0] a,
+	output signed [7:0] y,
 );
-    wire [7:0] mul;
-	assign mul = a * 4'd6;
-	assign y = mul / 8'd3;
+    wire signed [7:0] mul;
+	assign mul = a * 4'sd6;
+	assign y = mul / 8'sd6;
+endmodule
+EOT
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$div
+design -reset
+
+# b negative, c positive
+read_verilog <<EOT
+module top(
+	input signed [3:0] a,
+	output signed [7:0] y,
+);
+    wire signed [7:0] mul;
+	assign mul = a * -4'sd6;
+	assign y = mul / 8'sd3;
+endmodule
+EOT
+equiv_opt -assert peepopt
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 0 t:$div
+design -reset
+
+# b positive, c negative
+read_verilog <<EOT
+module top(
+	input signed [3:0] a,
+	output signed [7:0] y,
+);
+    wire signed [7:0] mul;
+	assign mul = a * 4'sd6;
+	assign y = mul / -8'sd3;
 endmodule
 EOT
 equiv_opt -assert peepopt
@@ -169,40 +221,21 @@ design -reset
 # select -assert-count 1 t:$div
 # design -reset
 
-# No transform when b only divisible by c if c misinterpreted as unsigned
+# No transform when b only divisible by c if b misinterpreted as unsigned
+# b 1001 is -7 but 9 misinterpreted
+# c 11 is 3
 read_verilog <<EOT
 module top(
 	input signed [3:0] a,
 	output signed [7:0] y,
 );
     wire signed [7:0] mul;
-	assign mul = a * 4'sd6;
-	assign y = mul / 3'sb110;
+	assign mul = a * 4'sb1001;
+	assign y = mul / 8'sb11;
 endmodule
 EOT
 equiv_opt -assert peepopt
-# design -load postopt
-# show
-# select -assert-count 1 t:$mul
-# select -assert-count 1 t:$div
-# design -reset
-
-# No transform when b only divisible by c if b misinterpreted as unsigned
-# read_verilog <<EOT
-# module top(
-# 	input signed [3:0] a,
-# 	output signed [7:0] y,
-# );
-#     wire signed [7:0] mul;
-# 	assign mul = a * -4'sd8;
-# 	assign y = mul / 8'sd2;
-# endmodule
-# EOT
-# dump
-# peepopt
-# show
-# equiv_opt -assert peepopt
-# design -load postopt
-# select -assert-count 1 t:$mul
-# select -assert-count 1 t:$div
-# design -reset
+design -load postopt
+select -assert-count 1 t:$mul
+select -assert-count 1 t:$div
+design -reset