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atmega32: Add ATmega32 and ATmega324p support. Implement simpler-api branch #138

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atmega32: Add ATmega32 and ATmega324p support. Implement simpler-api branch #138

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6f0ba2b
ATmega32: Refactor 328p-based files into separate files, add in basic…
jamesrwaugh Jan 30, 2023
5ec4459
Wip: Getting ATmega32 values in for USART, tests failing
jamesrwaugh Feb 2, 2023
8d13edd
ATmega32: More work on separating out USART to compose off of 328p
jamesrwaugh Feb 4, 2023
783b77a
ATmega32: merge work from simpler-api to split up chip config, standa…
jamesrwaugh Feb 7, 2023
922c6be
Correct interrupt vectors for many 324p parts
jamesrwaugh Feb 13, 2023
b374c38
Atmega32: Add in more 324-speciic mappings fr GPIO and SPI. 20MHZ clo…
jamesrwaugh Feb 14, 2023
8a893e0
ATmega32: Add Uart tests, fix bugs from tests, thanks tests.
jamesrwaugh Feb 14, 2023
1bb309f
Add another 32 USART test
jamesrwaugh Feb 14, 2023
522eb06
Clean up a bit
jamesrwaugh Feb 17, 2023
748add2
Merge review: type for createAvr, options, and fix 2560 export
jamesrwaugh Feb 25, 2023
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Add another 32 USART test
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@jamesrwaugh
jamesrwaugh committed Feb 14, 2023
commit 1bb309f544adc50fe52e40ed659c3cb7a81a4cc8
13 changes: 12 additions & 1 deletion src/peripherals/usart_atmega32.spec.ts
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Original file line number Diff line number Diff line change
Expand Up @@ -31,10 +31,21 @@ describe('ATmege32 USART', () => {
const usart = new AVRUSARTATmega32(cpu, usart0Config, FREQ_16MHZ);
cpu.writeData(usart0Config.UCSRC, usart0Config.UCSRC_URSEL | 0x40);
cpu.writeData(usart0Config.UCSRC, 0x0a);
cpu.cycles += 1;
expect(cpu.readData(usart0Config.UCSRC)).toEqual(0x0a);
cpu.cycles += 1;
expect(cpu.readData(usart0Config.UCSRC)).toEqual(0x40);
});

it('resets the sequential read after multiple cycles', () => {
const cpu = new CPU(new Uint16Array(1024));
cpu.cycles = 100;
const usart = new AVRUSARTATmega32(cpu, usart0Config, FREQ_16MHZ);
cpu.writeData(usart0Config.UCSRC, usart0Config.UCSRC_URSEL | 0x40);
cpu.writeData(usart0Config.UCSRC, 0x0a);
expect(cpu.readData(usart0Config.UCSRC)).toEqual(0x0a);
cpu.cycles += 1;
cpu.cycles += 1;
expect(cpu.readData(usart0Config.UCSRC)).toEqual(0x0a);
});
});
});