Add fs_mark benchmark and fix the bug of loaded registers process whe…

backend/remill/include/remill/BC/InstructionLifter.h

@@ -159,6 +159,7 @@ class EcvReg {
   static std::pair<EcvReg, EcvRegClass> GetRegInfo(const std::string &_reg_name);
 
   std::string GetRegName(EcvRegClass ecv_reg_class) const;
+  std::string GetWideRegName() const;
   bool CheckPassedArgsRegs() const;
   bool CheckPassedReturnRegs() const;
 

backend/remill/include/remill/BC/TraceLifter.h

@@ -236,11 +236,11 @@ class VirtualRegsOpt {
 
   llvm::Type *GetLLVMTypeFromRegZ(EcvRegClass ecv_reg_class);
   llvm::Type *GetWholeLLVMTypeFromRegZ(EcvReg);
-  EcvRegClass GetRegZFromLLVMType(llvm::Type *value_type);
+  EcvRegClass GetRegClassFromLLVMType(llvm::Type *value_type);
   llvm::Value *GetValueFromTargetBBAndReg(llvm::BasicBlock *target_bb, llvm::BasicBlock *request_bb,
                                           std::pair<EcvReg, EcvRegClass> ecv_reg_info);
   llvm::Value *CastFromInst(EcvReg target_ecv_reg, llvm::Value *from_inst, llvm::Type *to_inst_ty,
-                            llvm::Instruction *inst_at_before, llvm::Value *to_inst = nullptr);
+                            llvm::Instruction *inst_at_before);
 
   llvm::Value *GetRegValueFromCacheMap(
       EcvReg target_ecv_reg, llvm::Type *to_type, llvm::Instruction *inst_at_before,

backend/remill/lib/Arch/AArch64/Arch.cpp

@@ -4456,7 +4456,10 @@ bool TryDecodeCSEL_64_CONDSEL(const InstData &data, Instruction &inst) {
 
 // FCSEL  <Sd>, <Sn>, <Sm>, <cond>
 bool TryDecodeFCSEL_S_FLOATSEL(const InstData &data, Instruction &inst) {
-  return false;
+  inst.sema_func_arg_type = SemaFuncArgType::Nothing;
+  DecodeConditionalRegSelect(data, inst, kRegS, 3);
+  AddEcvNZCVOperand(inst, kActionRead);
+  return true;
 }
 
 // FCSEL  <Dd>, <Dn>, <Dm>, <cond>

backend/remill/lib/Arch/AArch64/Semantics/COND.cpp

@@ -38,12 +38,13 @@ DEF_SEM_U64(CSEL64, R64 src1, R64 src2, R64 ecv_nzcv_src) {
   return check_cond(Read(ecv_nzcv_src)) ? Read(src1) : Read(src2);
 }
 
-// FCSEL  <Dd>, <Dn>, <Dm>, <cond>
+// FCSEL  <Sd>, <Sn>, <Sm>, <cond>
 template <uint64_t (*check_cond)(uint64_t ecv_nzcv)>
 DEF_SEM_F32(FCSEL32, RF32 src1, RF32 src2, R64 ecv_nzcv_src) {
   return check_cond(Read(ecv_nzcv_src)) ? Read(src1) : Read(src2);
 }
 
+// FCSEL  <Dd>, <Dn>, <Dm>, <cond>
 template <uint64_t (*check_cond)(uint64_t ecv_nzcv)>
 DEF_SEM_F64(FCSEL64, RF64 src1, RF64 src2, R64 ecv_nzcv_src) {
   return check_cond(Read(ecv_nzcv_src)) ? Read(src1) : Read(src2);
@@ -72,6 +73,7 @@ DEF_COND_ISEL(CSEL_32_CONDSEL, CSEL32)  // CSEL  <Wd>, <Wn>, <Wm>, <cond>
 DEF_COND_ISEL(CSEL_64_CONDSEL, CSEL64)  // CSEL  <Xd>, <Xn>, <Xm>, <cond>
 
 DEF_COND_ISEL(FCSEL_D_FLOATSEL, FCSEL64)  // FCSEL  <Dd>, <Dn>, <Dm>, <cond>
+DEF_COND_ISEL(FCSEL_S_FLOATSEL, FCSEL64)  // FCSEL  <Sd>, <Sn>, <Sm>, <cond>
 
 namespace {
 

backend/remill/lib/Arch/AArch64/Semantics/SIMD.cpp

@@ -97,17 +97,15 @@ DEF_SEM_U64(FMOV_VectorToUInt64, VIu64v2 src) {
   return val;
 }
 
-// DEF_SEM(FMOV_UInt64ToVector, VI128 dst, R64 src) {
-//   auto val = Read(src);
-//   VIu64v2 tmpv = {};
-//   tmpv = UInsertV64(tmpv, 0, UExtractV64(UReadVI64(dst), 0));
-//   tmpv = UInsertV64(tmpv, 1, val);
-//   UWriteV64(dst, tmpv);
-// }
+DEF_SEM_F64(FMOV_UInt64ToVector, R64 src) {
+  auto val = Read(src);
+  auto float_valp = (float64_t *) (&val);
+  return *float_valp;
+}
 }  // namespace
 
 DEF_ISEL(FMOV_64VX_FLOAT2INT) = FMOV_VectorToUInt64;
-// DEF_ISEL(FMOV_V64I_FLOAT2INT) = FMOV_UInt64ToVector
+DEF_ISEL(FMOV_V64I_FLOAT2INT) = FMOV_UInt64ToVector;
 
 namespace {
 
@@ -122,10 +120,7 @@ namespace {
     return vec; \
   }  // namespace
 
-MAKE_DUP(8)
-MAKE_DUP(16)
-MAKE_DUP(32)
-MAKE_DUP(64)
+MAKE_DUP(8) MAKE_DUP(16) MAKE_DUP(32) MAKE_DUP(64)
 
 #undef MAKE_DUP
 

backend/remill/lib/BC/InstructionLifter.cpp

@@ -110,6 +110,45 @@ std::pair<EcvReg, EcvRegClass> EcvReg::GetRegInfo(const std::string &_reg_name)
   std::terminate();
 }
 
+std::string EcvReg::GetWideRegName() const {
+  if (number <= 31) {
+    std::string reg_name;
+    switch (reg_kind) {
+      case RegKind::General: reg_name = "X"; break;
+      case RegKind::Vector: reg_name = "V"; break;
+      case RegKind::Special:
+      default: LOG(FATAL) << "[Bug]: number must be 31 or less at GetWideRegName."; break;
+    }
+    reg_name += std::to_string(number);
+    return reg_name;
+  } else if (SP_ORDER == number) {
+    return "SP";
+  } else if (PC_ORDER == number) {
+    return "PC";
+  } else if (STATE_ORDER == number) {
+    return "STATE";
+  } else if (RUNTIME_ORDER == number) {
+    return "RUNTIME";
+  } else if (BRANCH_TAKEN_ORDER == number) {
+    return "BRANCH_TAKEN";
+  } else if (ECV_NZCV_ORDER == number) {
+    return "ECV_NZCV";
+  } else if (IGNORE_WRITE_TO_WZR_ORDER == number) {
+    return "IGNORE_WRITE_TO_WZR";
+  } else if (IGNORE_WRITE_TO_XZR_ORDER == number) {
+    return "IGNORE_WRITE_TO_XZR";
+  } else if (MONITOR_ORDER == number) {
+    return "MONITOR";
+  } else if (WZR_ORDER == number) {
+    return "WZR";
+  } else if (XZR_ORDER == number) {
+    return "XZR";
+  }
+
+  LOG(FATAL) << "[Bug]: Reach the unreachable code at EcvReg::GetWideRegName.";
+  return "";
+}
+
 std::string EcvReg::GetRegName(EcvRegClass ecv_reg_class) const {
   static std::unordered_map<EcvRegClass, std::string> EcvRegClassRegNameMap = {
       {EcvRegClass::RegW, "W"},     {EcvRegClass::RegX, "X"},     {EcvRegClass::RegB, "B"},