FIX

frontends/concrete-python/concrete/fhe/extensions/synthesis/luts_to_fhe.py

@@ -231,7 +231,7 @@ def repack_scaled_bits(
         assert scale & (scale - 1) == 0  # is power of 2
         weight = 2**i // scale
         max_weight = max(max_weight, weight)
-        if isinstance(value.result, arith.ConstantOp):
+        if isinstance(value, Conversion) and isinstance(value.result, arith.ConstantOp):
             # clear mul-mul is not supported
             constants_sum += int(str(value.result.attributes["value"]).split(":")[0]) * weight
             continue
@@ -261,8 +261,8 @@ def repack_scaled_bits(
             repacked_bits = context.add(add.type, repacked_bits, add)
     assert repacked_bits is not None
     if constants_sum != 0:
-        constants_sum = context.constant(context.i(repacked_bits.type.bit_width + 1), constants_sum)
-        repacked_bits = context.add(repacked_bits.type, repacked_bits, constants_sum)
+        constant = context.constant(context.i(repacked_bits.type.bit_width + 1), constants_sum)
+        repacked_bits = context.add(repacked_bits.type, repacked_bits, constant)
     extra_bits = arg_max_bit_width - bit_width
     if extra_bits > 0 and before_tlu and RESCALE_BEFORE_TLU:
         repacked_bits = context.safe_reduce_precision(repacked_bits, bit_width)

frontends/concrete-python/concrete/fhe/extensions/synthesis/verilog_source.py

@@ -5,8 +5,6 @@
 from dataclasses import dataclass
 from typing import Dict, List, Tuple
 
-import numpy as np
-
 
 @dataclass
 class Ty:

frontends/concrete-python/tests/execution/test_synthesis.py

@@ -333,7 +333,7 @@ def tlu(a, b):
     time_0 = time.time()
     circuit = tlu.compile(inputset, conf)
     time_1 = time.time()
-    assert time_1 - time_0 < 60
+    assert time_1 - time_0 < 120
 
     assert circuit.mlir.count("lsb") >= 2 * bit_width
     assert circuit.mlir.count("table") > 1