soc: amd: acp_6_0: add support for AMD ACP_6_0 soc.

Add a common part for AMD board ACP_6_0_ADSP.

Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.

This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.

Signed-off-by: DineshKumar Kalva <[email protected]>

dts/xtensa/amd/acp_6_0.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			reg = <0>;
+		};
+	};
+};

soc/amd/acp_6_0/CMakeLists.txt

@@ -0,0 +1,15 @@
+if(CONFIG_SOC_ACP_6_0)
+  zephyr_include_directories(adsp)
+  add_subdirectory(adsp)
+# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
+add_custom_target(zephyr.ri ALL
+  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+)
+add_custom_command(
+  OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+  COMMENT "west sign --if-tool-available --tool rimage ..."
+  COMMAND  west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
+  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
+)
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")
+endif()

soc/amd/acp_6_0/Kconfig

@@ -0,0 +1,7 @@
+# Copyright 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+config SOC_ACP_6_0
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select ATOMIC_OPERATIONS_BUILTIN

soc/amd/acp_6_0/Kconfig.defconfig

@@ -0,0 +1,28 @@
+# Copyright (c) 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ACP_6_0
+config DCACHE_LINE_SIZE
+default 128
+
+config CACHE_MANAGEMENT
+default n
+
+config XTENSA_TIMER
+default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+default 600000000 if XTENSA_TIMER
+
+config KERNEL_ENTRY
+default "__start"
+
+config MULTI_LEVEL_INTERRUPTS
+default n
+
+config 2ND_LEVEL_INTERRUPTS
+default n
+
+config KERNEL_ENTRY
+default "__start"
+endif

soc/amd/acp_6_0/Kconfig.soc

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ACP_6_0
+	bool
+	default "BOARD_ACP_6_0_ADSP"
+
+config SOC
+	default "acp_6_0" if SOC_ACP_6_0
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "amd_acp_6_0_adsp"

soc/amd/acp_6_0/adsp/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright (c) 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_include_directories(include)

soc/amd/acp_6_0/adsp/_soc_inthandlers.h

@@ -0,0 +1,165 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+/*
+ * THIS FILE WAS AUTOMATICALLY GENERATED.  DO NOT EDIT.
+ *
+ * Functions here are designed to produce efficient code to
+ * search an Xtensa bitmask of interrupts, inspecting only those bits
+ * declared to be associated with a given interrupt level.  Each
+ * dispatcher will handle exactly one flagged interrupt, in numerical
+ * order (low bits first) and will return a mask of that bit that can
+ * then be cleared by the calling code.  Unrecognized bits for the
+ * level will invoke an error handler.
+ */
+
+#include <xtensa/config/core-isa.h>
+#include <zephyr/sys/util.h>
+#include <zephyr/sw_isr_table.h>
+
+#if !defined(XCHAL_INT0_LEVEL) || XCHAL_INT0_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT1_LEVEL) || XCHAL_INT1_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT6_LEVEL) || XCHAL_INT6_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT8_LEVEL) || XCHAL_INT8_LEVEL != 1
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT2_LEVEL) || XCHAL_INT2_LEVEL != 2
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT3_LEVEL) || XCHAL_INT3_LEVEL != 3
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT4_LEVEL) || XCHAL_INT4_LEVEL != 4
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT5_LEVEL) || XCHAL_INT5_LEVEL != 5
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+#if !defined(XCHAL_INT7_LEVEL) || XCHAL_INT7_LEVEL != 7
+#error core-isa.h interrupt level does not match dispatcher!
+#endif
+
+static inline int _xtensa_handle_one_int1(unsigned int mask)
+{
+	int irq;
+
+	if (mask & 0x3) {
+		if (mask & BIT(0)) {
+			mask = BIT(0);
+			irq = 0;
+			goto handle_irq;
+		}
+		if (mask & BIT(1)) {
+			mask = BIT(1);
+			irq = 1;
+			goto handle_irq;
+		}
+	} else {
+		if (mask & BIT(6)) {
+			mask = BIT(6);
+			irq = 6;
+			goto handle_irq;
+		}
+		if (mask & BIT(8)) {
+			mask = BIT(8);
+			irq = 8;
+			goto handle_irq;
+		}
+	}
+	return 0;
+handle_irq:
+	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+	return mask;
+}
+
+static inline int _xtensa_handle_one_int2(unsigned int mask)
+{
+	int irq;
+
+	if (mask & BIT(2)) {
+		mask = BIT(2);
+		irq = 2;
+		goto handle_irq;
+	}
+	return 0;
+handle_irq:
+	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+	return mask;
+}
+
+static inline int _xtensa_handle_one_int3(unsigned int mask)
+{
+	int irq;
+
+	if (mask & BIT(3)) {
+		mask = BIT(3);
+		irq = 3;
+		goto handle_irq;
+	}
+	return 0;
+handle_irq:
+	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+	return mask;
+}
+
+static inline int _xtensa_handle_one_int4(unsigned int mask)
+{
+	int irq;
+
+	if (mask & BIT(4)) {
+		mask = BIT(4);
+		irq = 4;
+		goto handle_irq;
+	}
+	return 0;
+handle_irq:
+	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+	return mask;
+}
+
+static inline int _xtensa_handle_one_int5(unsigned int mask)
+{
+	int irq;
+
+	if (mask & BIT(5)) {
+		mask = BIT(5);
+		irq = 5;
+		goto handle_irq;
+	}
+	return 0;
+handle_irq:
+	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+	return mask;
+}
+
+static inline int _xtensa_handle_one_int7(unsigned int mask)
+{
+	int irq;
+
+	if (mask & BIT(7)) {
+		mask = BIT(7);
+		irq = 7;
+		goto handle_irq;
+	}
+	return 0;
+handle_irq:
+	_sw_isr_table[irq].isr(_sw_isr_table[irq].arg);
+	return mask;
+}
+
+static inline int _xtensa_handle_one_int0(unsigned int mask)
+{
+	return 0;
+}
+static inline int _xtensa_handle_one_int6(unsigned int mask)
+{
+	return 0;
+}

soc/amd/acp_6_0/adsp/include/adsp/cache.h

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __COMMON_ADSP_CACHE_H__
+#define __COMMON_ADSP_CACHE_H__
+#include <xtensa/hal.h>
+#endif

soc/amd/acp_6_0/adsp/include/adsp/io.h

@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INCLUDE_IO__
+#define __INCLUDE_IO__
+
+#include <stdint.h>
+#include <soc/memory.h>
+#include <zephyr/sys/sys_io.h>
+#include <zephyr/arch/common/sys_io.h>
+
+static inline uint32_t io_reg_read(uint32_t reg)
+{
+	return sys_read32(reg);
+}
+
+static inline void io_reg_write(uint32_t reg, uint32_t val)
+{
+	sys_write32(val, reg);
+}
+
+static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
+{
+	io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
+}
+
+static inline uint16_t io_reg_read16(uint32_t reg)
+{
+	return sys_read16(reg);
+}
+
+static inline void io_reg_write16(uint32_t reg, uint16_t val)
+{
+	sys_write16(val, reg);
+}
+
+#endif