Add support for AMD ACP_6_0 ADSP

CODEOWNERS

@@ -133,6 +133,7 @@
 /boards/arm64/intel_socfpga_agilex_socdk/ @siclim @ngboonkhai
 /boards/arm64/intel_socfpga_agilex5_socdk/ @teikheng @gdengi
 /boards/arm64/rcar_*/                     @lorc @xakep-amatop
+/boards/amd/acp_6_0_adsp/               @dineshkumar.kalva @basavaraj.hiregoudar
 # All cmake related files
 /doc/develop/tools/coccinelle.rst                @himanshujha199640 @JuliaLawall
 /doc/services/device_mgmt/smp_protocol.rst  @de-nordic @nordicjm

boards/amd/acp_6_0_adsp/Kconfig.acp_6_0_adsp

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ACP_6_0_ADSP
+select SOC_ACP_6_0

boards/amd/acp_6_0_adsp/acp_6_0_acp_adsp.dts

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <amd/acp_6_0.dtsi>
+
+/ {
+	model = "AMD ACP_6_0  Audio DSP";
+	compatible = "acp_6_0";
+};

boards/amd/acp_6_0_adsp/acp_6_0_adsp.yml

@@ -0,0 +1,14 @@
+#
+# Copyright 2024 AMD
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+identifier: acp_6_0_adsp/acp_6_0
+name: AMD ACP6.0  Audio DSP
+type: mcu
+arch: xtensa
+toolchain:
+  - zephyr
+  - xcc
+vendor: amd

boards/amd/acp_6_0_adsp/acp_6_0_adsp_defconfig

@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_GEN_ISR_TABLES=y
+CONFIG_GEN_IRQ_VECTOR_TABLE=y
+CONFIG_XTENSA_RESET_VECTOR=y
+CONFIG_OUTPUT_SYMBOLS=y
+CONFIG_MULTI_LEVEL_INTERRUPTS=n
+CONFIG_2ND_LEVEL_INTERRUPTS=n
+CONFIG_DCACHE_LINE_SIZE_DETECT=n
+CONFIG_DCACHE_LINE_SIZE=128

boards/amd/acp_6_0_adsp/board.cmake

@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: Apache-2.0
+board_set_flasher_ifnset(misc-flasher)
+board_finalize_runner_args(misc-flasher)
+board_set_rimage_target(rmb)

boards/amd/acp_6_0_adsp/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: acp_6_0_adsp
+  full_name: ACP 6.0 Xtensa Audio DSP
+  vendor: amd
+  socs:
+    - name: acp_6_0

boards/amd/acp_6_0_adsp/doc/index.rst

@@ -0,0 +1,109 @@
+.. zephyr:board:: acp_6_0_adsp
+
+Overview
+********
+
+ACP 6.0 is Audio co-processor in AMD SoC based on HiFi5 DSP Xtensa Architecture,
+Zephyr OS is ported to run various audio and speech use cases on
+the SOF based framework.
+
+SOF can be built with either Zephyr or Cadence's proprietary
+Xtensa OS (XTOS) and run on a ACP 6.0 AMD platforms.
+
+Hardware
+********
+
+- Board features:
+
+  - RAM: 1.75MB HP SRAM & 512KB configurable IRAM/DRAM
+  - Audio Interfaces:
+
+      - 1 x SP (I2S, PCM),
+      - 1 x BT (I2S, PCM),
+      - 1 x HS (I2S, PCM),
+      - DMIC
+
+Supported Features
+==================
+
+The following hardware features are supported:
+
++-----------+------------+-------------------------------------+
+| Interface | Controller | Driver/Component                    |
++===========+============+=====================================+
+| I2S       | on-chip    | I2S controller                      |
++-----------+------------+-------------------------------------+
+| DMIC(PDM) | on-chip    | PDM controller                      |
++-----------+------------+-------------------------------------+
+
+System Clock
+============
+
+The ACP 6.0 SoC operates with an audio clock frequency ranging from 200 to 800 MHz.
+
+System requirements
+*******************
+
+Xtensa Toolchain (optional)
+===========================
+
+The Zephyr SDK provides GCC-based toolchains necessary to build Zephyr for
+the AMD ACP boards. For users looking for higher optimization levels,
+building with the proprietary Xtensa toolchain from Cadence
+might be preferable.
+
+The following instructions assume you have purchased and
+installed the toolchain(s) and core(s) for your board following
+instructions from Xtensa documentation.
+
+If you choose to build with the Xtensa toolchain instead of the Zephyr SDK, set
+the following environment variables specific to the board in addition to the
+Xtensa toolchain environment variable listed below.
+
+First, make sure, the necessary license is available from
+Cadence and set the license variables as per the instruction from Cadence.
+Next, set the following environment variables:
+
+The bottom three variables are specific to acp_6_0.
+
+.. code-block:: shell
+
+   export XTENSA_TOOLCHAIN_PATH="tools installed path"
+   export XTENSA_BUILDS_DIR="user build directory path"
+   export ZEPHYR_TOOLCHAIN_VARIANT=xcc
+   export TOOLCHAIN_VER=RI-2019.1-linux
+   export XTENSA_CORE=LX7_HiFi5_PROD
+
+Programming and Debugging
+*************************
+
+Building
+========
+
+Build as usual.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/hello_world
+   :board: acp_6_0_adsp/acp_6_0
+   :goals: build
+
+Flashing
+========
+
+AMD supports only signed images flashing on ACP 6.0 platforms
+through ACP Linux Driver.
+
+The following boot sequence messages can be observed in dmesg
+
+   -  booting DSP firmware
+   -  ACP_DSP0_RUNSTALL : 0x0
+   -  ipc rx: 0x70000000
+   -  Firmware info: version 2:11:99-03a9d
+   -  Firmware: ABI 3:29:1 Kernel ABI 3:23:0
+   -  mailbox upstream 0x0 - size 0x400
+   -  mailbox downstream 0x400 - size 0x400
+   -  stream region 0x1000 - size 0x400
+   -  debug region 0x800 - size 0x400
+   -  fw_state change: 3 -> 6
+   -  ipc rx done: 0x70000000
+   -  firmware boot complete

dts/xtensa/amd/acp_6_0.dtsi

@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2024 AMD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <xtensa/xtensa.dtsi>
+#include <mem.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "cdns,tensilica-xtensa-lx7";
+			reg = <0>;
+		};
+	};
+};

scripts/west_commands/sign.py

@@ -470,7 +470,7 @@ def sign(self, command, build_dir, build_conf, formats):
         kernel_name = build_conf.get('CONFIG_KERNEL_BIN_NAME', 'zephyr')
 
         # TODO: make this a new sign.py --bootloader option.
-        if target in ('imx8', 'imx8m', 'imx8ulp', 'imx95'):
+        if target in ('imx8', 'imx8m', 'imx8ulp', 'imx95', 'rmb'):
             bootloader = None
             kernel = str(b / 'zephyr' / f'{kernel_name}.elf')
             out_bin = str(b / 'zephyr' / f'{kernel_name}.ri')

soc/amd/acp_6_0/CMakeLists.txt

@@ -0,0 +1,11 @@
+# See detailed comments in soc/xtensa/intel_adsp/common/CMakeLists.txt
+add_custom_target(zephyr.ri ALL
+  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+)
+add_custom_command(
+  OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
+  COMMENT "west sign --if-tool-available --tool rimage ..."
+  COMMAND  west sign --if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR} ${WEST_SIGN_OPTS}
+  DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
+)
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/adsp/linker.ld CACHE INTERNAL "")

soc/amd/acp_6_0/Kconfig

@@ -0,0 +1,8 @@
+# Copyright 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+config SOC_ACP_6_0
+	select XTENSA
+	select XTENSA_GEN_HANDLERS
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select ATOMIC_OPERATIONS_BUILTIN

soc/amd/acp_6_0/Kconfig.defconfig

@@ -0,0 +1,25 @@
+# Copyright (c) 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_ACP_6_0
+config DCACHE_LINE_SIZE
+	default 128
+
+config CACHE_MANAGEMENT
+	default n
+
+config XTENSA_TIMER
+	default y
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 600000000 if XTENSA_TIMER
+
+config MULTI_LEVEL_INTERRUPTS
+	default n
+
+config 2ND_LEVEL_INTERRUPTS
+	default n
+
+config KERNEL_ENTRY
+	default "__start"
+endif

soc/amd/acp_6_0/Kconfig.soc

@@ -0,0 +1,13 @@
+# Copyright (c) 2024 AMD
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC_ACP_6_0
+	bool
+	default "BOARD_ACP_6_0_ADSP"
+
+config SOC
+	default "acp_6_0" if SOC_ACP_6_0
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "amd_acp_6_0_adsp"