i2c: stm32: dma enhancement

drivers/i2c/Kconfig.stm32

@@ -55,4 +55,10 @@ config I2C_STM32_V2_TIMING
 	help
 	  Enable STM32 driver bus to calculate the Timing.
 
+config I2C_DMA
+	bool "DMA support"
+	depends on I2C_STM32_V2
+	help
+	  Enable DMA support for the STM32 I2C driver.
+
 endif # I2C_STM32

drivers/i2c/i2c_ll_stm32.c

@@ -5,6 +5,8 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
+#include <zephyr/drivers/dma.h>
+#include <zephyr/drivers/dma/dma_stm32.h>
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/pm/device.h>
@@ -143,7 +145,8 @@ static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
 			      uint8_t num_msgs, uint16_t slave)
 {
 	struct i2c_stm32_data *data = dev->data;
-	struct i2c_msg *current, *next;
+	struct i2c_msg *current;
+	struct i2c_msg *next = NULL;
 	int ret = 0;
 
 	/* Check for validity of all messages, to prevent having to abort
@@ -201,13 +204,7 @@ static int i2c_stm32_transfer(const struct device *dev, struct i2c_msg *msg,
 	current = msg;
 
 	while (num_msgs > 0) {
-		uint8_t *next_msg_flags = NULL;
-
-		if (num_msgs > 1) {
-			next = current + 1;
-			next_msg_flags = &(next->flags);
-		}
-		ret = stm32_i2c_transaction(dev, *current, next_msg_flags, slave);
+		ret = stm32_i2c_transaction(dev, *current, next ? &(next->flags) : NULL, slave);
 		if (ret < 0) {
 			break;
 		}
@@ -391,6 +388,11 @@ static int i2c_stm32_init(const struct device *dev)
 	cfg->irq_config_func(dev);
 #endif
 
+#ifdef CONFIG_I2C_DMA
+	k_sem_init(&data->dma_rx_sem, 1, K_SEM_MAX_LIMIT);
+	k_sem_init(&data->dma_tx_sem, 1, K_SEM_MAX_LIMIT);
+#endif
+
 	data->is_configured = false;
 	data->mode = I2CSTM32MODE_I2C;
 
@@ -535,6 +537,52 @@ void i2c_stm32_smbalert_disable(const struct device *dev)
 }
 #endif /* CONFIG_SMBUS_STM32 */
 
+#ifdef CONFIG_I2C_DMA
+/* This function is executed in the interrupt context */
+static void dma_rx_callback(const struct device *dma_dev, void *user_data,
+                            uint32_t channel, int status)
+{
+    struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data;
+
+    switch (status) {
+        case DMA_STATUS_COMPLETE:
+                data->current.is_err = 0;
+				dma_stop(dma_dev, channel);
+                break;
+        case DMA_STATUS_BLOCK:
+                break;
+        default:
+                data->current.is_err = 1;
+                break;
+    }
+
+    k_sem_give(&data->device_sync_sem);
+}
+
+/* This function is executed in the interrupt context */
+static void dma_tx_callback(const struct device *dma_dev, void *user_data,
+                            uint32_t channel, int status)
+{
+    struct i2c_stm32_data *data = (struct i2c_stm32_data *)user_data;
+
+    switch (status) {
+        case DMA_STATUS_COMPLETE:
+                data->current.is_err = 0;
+				dma_stop(dma_dev, channel);
+                break;
+        case DMA_STATUS_BLOCK:
+                break;
+        default:
+                data->current.is_err = 1;
+                break;
+    }
+
+    LOG_DBG("Giving semaphore");
+    k_sem_give(&data->device_sync_sem);
+}
+
+#endif /* CONFIG_I2C_DMA */
+
 /* Macros for I2C instance declaration */
 
 #ifdef CONFIG_I2C_STM32_INTERRUPT
@@ -582,6 +630,46 @@ static void i2c_stm32_irq_config_func_##index(const struct device *dev)	\
 
 #endif /* CONFIG_I2C_STM32_INTERRUPT */
 
+#ifdef CONFIG_I2C_DMA
+
+#define I2C_DMA_INIT(index, dir)                                                                   \
+    .dev_dma_##dir = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),                                \
+                                 (DEVICE_DT_GET(STM32_DMA_CTLR(index, dir))), (NULL)),             \
+    .dma_##dir##_channel = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),                          \
+                                       (DT_INST_DMAS_CELL_BY_NAME(index, dir, channel)), (-1)),
+
+#define I2C_DMA_SLOT_INIT(index, dir)                                                              \
+    .dma_slot = COND_CODE_1(DT_INST_DMAS_HAS_NAME(index, dir),                                     \
+                            (DT_INST_DMAS_CELL_BY_NAME(index, dir, slot)), (0))
+
+#define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr)               \
+.dma_##dir##_cfg = {                                                                               \
+    I2C_DMA_SLOT_INIT(index, dir),                                                                 \
+    .channel_direction = STM32_DMA_CONFIG_DIRECTION(STM32_DMA_CHANNEL_CONFIG(index, dir)),         \
+    .source_data_size = STM32_DMA_CONFIG_##src##_DATA_SIZE(                                        \
+                            STM32_DMA_CHANNEL_CONFIG(index, dir)),                                 \
+    .dest_data_size = STM32_DMA_CONFIG_##dest##_DATA_SIZE(                                         \
+                            STM32_DMA_CHANNEL_CONFIG(index, dir)),                                 \
+    .source_burst_length = 1,                                                                      \
+    .dest_burst_length = 1,                                                                        \
+    .channel_priority = STM32_DMA_CONFIG_PRIORITY(STM32_DMA_CHANNEL_CONFIG(index, dir)),           \
+    .dma_callback = dma_##dir##_callback,                                                          \
+},                                                                                                 \
+.dma_##dir##_blk_cfg = {                                                                           \
+            .source_addr_adj = src_addr_incr,                                                      \
+            .dest_addr_adj = dest_addr_incr,                                                       \
+},
+
+#else
+
+#define I2C_DMA_INIT(index, dir)
+
+#define I2C_DMA_SLOT_INIT(index, dir)
+
+#define I2C_DMA_CFG_INIT(index, name, dir, src, dest, src_addr_incr, dest_addr_incr)
+
+#endif
+
 #define STM32_I2C_INIT(index)						\
 STM32_I2C_IRQ_HANDLER_DECL(index);					\
 									\
@@ -607,6 +695,8 @@ static const struct i2c_stm32_config i2c_stm32_cfg_##index = {		\
 	IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2),		\
 		(.timings = (const struct i2c_config_timing *) i2c_timings_##index,\
 		 .n_timings = ARRAY_SIZE(i2c_timings_##index),))	\
+	I2C_DMA_INIT(index, tx) \
+	I2C_DMA_INIT(index, rx) \
 };									\
 									\
 static struct i2c_stm32_data i2c_stm32_dev_data_##index;		\

drivers/i2c/i2c_ll_stm32.h

@@ -15,6 +15,8 @@
 #include <zephyr/drivers/gpio.h>
 #endif /* CONFIG_I2C_STM32_BUS_RECOVERY */
 
+#include <zephyr/drivers/dma.h>
+
 typedef void (*irq_config_func_t)(const struct device *port);
 
 #if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_i2c_v2)
@@ -48,6 +50,12 @@ struct i2c_stm32_config {
 	const struct i2c_config_timing *timings;
 	size_t n_timings;
 #endif
+#ifdef CONFIG_I2C_DMA
+	const struct device *dev_dma_tx;
+	int32_t dma_tx_channel;
+	const struct device *dev_dma_rx;
+	int32_t dma_rx_channel;
+#endif /* CONFIG_I2C_DMA */
 };
 
 struct i2c_stm32_data {
@@ -91,6 +99,14 @@ struct i2c_stm32_data {
 	i2c_stm32_smbalert_cb_func_t smbalert_cb_func;
 	const struct device *smbalert_cb_dev;
 #endif
+#ifdef CONFIG_I2C_DMA
+	struct dma_config dma_tx_cfg;
+	struct dma_block_config dma_tx_blk_cfg;
+	struct k_sem dma_tx_sem;
+	struct dma_config dma_rx_cfg;
+	struct dma_block_config dma_rx_blk_cfg;
+	struct k_sem dma_rx_sem;
+#endif /* CONFIG_I2C_DMA */
 };
 
 int32_t stm32_i2c_transaction(const struct device *dev,

drivers/i2c/i2c_ll_stm32_v2.c

@@ -117,6 +117,42 @@ static struct stm32_i2c_timings_t i2c_valid_timing[STM32_I2C_VALID_TIMING_NBR];
 static uint32_t i2c_valid_timing_nbr;
 #endif /* CONFIG_I2C_STM32_V2_TIMING */
 
+#ifdef CONFIG_I2C_DMA
+static int configure_dma(const struct device *dma_dev, uint32_t dma_channel,
+			 struct dma_config *dma_cfg, struct dma_block_config *blk_cfg,
+			 uint32_t source_address, uint32_t dest_address, struct i2c_msg *msg,
+			 struct k_sem *dma_sem, const char *direction)
+{
+	if (!device_is_ready(dma_dev)) {
+		LOG_ERR("DMA device not ready for %s", direction);
+		return -ENODEV;
+	}
+
+	k_sem_take(dma_sem, K_FOREVER);
+
+	blk_cfg->source_address = source_address;
+	blk_cfg->dest_address = dest_address;
+	blk_cfg->block_size = msg->len;
+
+	dma_cfg->head_block = blk_cfg;
+	dma_cfg->block_count = 1;
+
+	int ret = dma_config(dma_dev, dma_channel, dma_cfg);
+	if (ret != 0) {
+		LOG_ERR("Problem setting up %s DMA: %d", direction, ret);
+		return ret;
+	}
+
+	ret = dma_start(dma_dev, dma_channel);
+	if (ret != 0) {
+		LOG_ERR("Problem starting %s DMA: %d", direction, ret);
+		return ret;
+	}
+
+	return 0;
+}
+#endif
+
 static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
 			    uint8_t *next_msg_flags, uint16_t slave,
 			    uint32_t transfer)
@@ -151,6 +187,48 @@ static inline void msg_init(const struct device *dev, struct i2c_msg *msg,
 #if defined(CONFIG_I2C_TARGET)
 		data->master_active = true;
 #endif
+
+#ifdef CONFIG_I2C_DMA
+		if (msg->len) {
+			if (msg->flags & I2C_MSG_READ) {
+				// Configure RX DMA
+				if (configure_dma(cfg->dev_dma_rx, cfg->dma_rx_channel,
+						  &data->dma_rx_cfg, &data->dma_rx_blk_cfg,
+						  LL_I2C_DMA_GetRegAddr(
+							  cfg->i2c, LL_I2C_DMA_REG_DATA_RECEIVE),
+						  (uint32_t)msg->buf, msg, &data->dma_rx_sem,
+						  "RX") != 0) {
+					return;
+				}
+				data->current.buf += msg->len;
+				data->current.len -= msg->len;
+				LL_I2C_EnableDMAReq_RX(i2c);
+			} else {
+				// Preload the TX register for the first byte
+
+				LL_I2C_TransmitData8(i2c, *data->current.buf);
+				data->current.buf++;
+				data->current.len--;
+
+				if (msg->len) {
+					// Configure TX DMA
+					if (configure_dma(
+						    cfg->dev_dma_tx, cfg->dma_tx_channel,
+						    &data->dma_tx_cfg, &data->dma_tx_blk_cfg,
+						    (uint32_t)msg->buf,
+						    LL_I2C_DMA_GetRegAddr(
+							    cfg->i2c, LL_I2C_DMA_REG_DATA_TRANSMIT),
+						    msg, &data->dma_tx_sem, "TX") != 0) {
+						return;
+					}
+					data->current.buf += msg->len;
+					data->current.len -= msg->len;
+					LL_I2C_EnableDMAReq_TX(i2c);
+				}
+			}
+		}
+#endif
+
 		LL_I2C_Enable(i2c);
 
 		LL_I2C_GenerateStartCondition(i2c);
@@ -209,6 +287,19 @@ static void stm32_i2c_master_mode_end(const struct device *dev)
 		LL_I2C_Disable(i2c);
 	}
 #endif
+
+#ifdef CONFIG_I2C_DMA
+	if (data->current.msg->flags & I2C_MSG_READ) {
+		dma_stop(cfg->dev_dma_rx, cfg->dma_rx_channel);
+		k_sem_give(&data->dma_rx_sem);
+		LL_I2C_DisableDMAReq_RX(i2c);
+	} else {
+		dma_stop(cfg->dev_dma_tx, cfg->dma_tx_channel);
+		k_sem_give(&data->dma_tx_sem);
+		LL_I2C_DisableDMAReq_TX(i2c);
+	}
+#endif
+
 	k_sem_give(&data->device_sync_sem);
 }
 
@@ -508,6 +599,19 @@ static void stm32_i2c_event(const struct device *dev)
 			LL_I2C_GenerateStopCondition(i2c);
 		} else {
 			stm32_i2c_disable_transfer_interrupts(dev);
+
+#ifdef CONFIG_I2C_DMA
+			if (data->current.msg->flags & I2C_MSG_READ) {
+				dma_stop(cfg->dev_dma_rx, cfg->dma_rx_channel);
+				k_sem_give(&data->dma_rx_sem);
+				LL_I2C_DisableDMAReq_RX(i2c);
+			} else {
+				dma_stop(cfg->dev_dma_tx, cfg->dma_tx_channel);
+				k_sem_give(&data->dma_tx_sem);
+				LL_I2C_DisableDMAReq_TX(i2c);
+			}
+#endif
+
 			k_sem_give(&data->device_sync_sem);
 		}
 	}

dts/bindings/i2c/st,stm32-i2c-v2.yaml

@@ -55,3 +55,17 @@ properties:
     description: |
       GPIO to which the I2C SDA signal is routed. This is only needed for
       I2C bus recovery support.
+
+  dmas:
+    type: phandle-array
+    description: |
+      Optional DMA channels used by the I2C peripheral. If specified, these
+      channels can be used to handle RX and TX transactions over DMA.
+    required: false
+
+  dma-names:
+    type: string-array
+    description: |
+      Names of the optional DMA channels. Expected values are "tx" for
+      the TX channel and "rx" for the RX channel.
+    required: false