drivers: clock_control: stm32 ll common: fix RCC pll disable

[bbyers-UBCO]

The clock_stm32_ll_common.c function set_up_plls calls LL_RCC_PLL_Disable(); and it was not waiting for the disable to complete before trying to configure the pll sysclock which creates a race condition for pll configuration. The wait for re-enabling the RCC pll is already there, it was just missing the wait for the disable before configuration.

[github-actions]

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[erwango]

Thanks @bbyers-UBCO !

Please fix the compliance issues reported by ci here.

[erwango]

Please fix indentation (we're using 8 char tabs)

[bbyers-UBCO]

Fixed. Also added the LL_RCC_PLL2_IsReady() check as @FRASTM mentioned.

[FRASTM]

Thanks for fixing that
LGTM after formatting the code

Probably that control loop should also apply anywhere a PLL is being disabled by LL_RCC_PLL1_Disable() or LL_RCC_PLL2_Disable() before any access to the PLL config register.