Semester: 2023 Spring
Lecturer: Prof. Yajun Yu
| # | Name | Description | Objectives |
|---|---|---|---|
| 1 | Full Adder | Combinational design of a full adder. Artifically set delays for simulation. | VDHL description for combinational logic circuit. A first glance of five simulation modes in Vivado. |
| 2 | Priority Decoder | A 16-4 encoder using two structures: cascade and tree-shaped. | Understand the impact of hardware architecture of combinational circuit. |
| 3 | Decimal Counter | A three-digit decimal counter. | Move from combinational circuit to sequential circuit. Two-segment coding style. |
| 4 | Fibonacci Series Calculator | A Fibonacci sequence calculator using Finite State Machine with Datapath (FSDM). Display the result using 7-segment tube. | FSMD design. Seven-segment display. |
| 5 | Step Motor | A drive circuit for the step motor with adjustbale speed and direction on FPGA board | The peripheral modules (Pmod) of Nexys4 DDR. The working principle of the step motor. |
| 6 | 16-bit multipliers | A 16-bit multiplier using three differnet structures: combinational design, repetitive-addition design and pipelined design. | Pipelined structure. Delay and throughput. Parameterized design. |
All the design is implemented on Xilinx Nexys4 DDR board，shown as follows.
Any comments are welcome!