RISC Processor Project - README

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Project Name: RISC Processor
Version: 1.0
Author: Akor Michael
Date: September 2023

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Table of Contents

1. Project Overview
2. Features
3. Folder Structure
4. Getting Started
5. Usage
6. Contributing
7. License
8. Contact

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Project Overview

This project implements a simple 16-bit RISC (Reduced Instruction Set Computing) processor in Verilog. The processor is designed for educational purposes, providing a platform for understanding the basic concepts of processor design, instruction sets, and digital logic.

The processor includes a small set of instructions, a control unit, and a datapath capable of executing basic arithmetic, logic, and memory operations. It can be simulated using Verilog HDL simulators, making it suitable for use in coursework, research, or as a starting point for more complex designs.

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Features

• 16-bit Architecture: The processor operates on 16-bit data and addresses.
• Basic Instruction Set: Supports load/store, arithmetic, logic, branch, and jump instructions.
• Modular Design: The processor is implemented in a modular fashion, making it easy to extend or modify.
• Testbench Included: A testbench is provided to simulate and verify the functionality of the processor.

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Folder Structure

The project is organized as follows:

risc-processor/
├── src/
│   ├── Risc_16_bit.v            # Top-level module
│   ├── Datapath_Unit.v          # Datapath module
│   ├── Control_Unit.v           # Control Unit module
│   ├── ALU.v                    # ALU module
│   ├── Instruction_Memory.v     # Instruction Memory module
│   ├── Data_Memory.v            # Data Memory module
│   └── GPRs.v                   # General Purpose Registers module
├── testbench/
│   ├── test_Risc_16_bit.v       # Testbench for the processor
│   └── simulation_time.v        # Simulation timing parameters
├── docs/
│   ├── Design_Specification.pdf # Design specification document
│   └── User_Manual.pdf          # User manual
└── README.md

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Getting Started

Prerequisites

• Verilog HDL Simulator: Ensure you have a Verilog HDL simulator installed (e.g., ModelSim, Vivado).
• Git: Version control system to clone the repository.

Installation

1. Clone the Repository:

   git clone https://github.com/Akor-Michael/RISC-Processor-16-Bit

2. Navigate to the Project Directory:

   cd risc-processor

3. Open the Project: Use your preferred Verilog HDL simulator to open the project files.

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Usage

1. Compile the Processor:

   • Open the Verilog source files in your simulator and compile them.

2. Run the Testbench:

   • Open test_Risc_16_bit.v in your simulator.
   • Run the simulation to verify the processor's functionality.

3. Analyze the Output:

   • Use waveform viewers or console outputs to analyze the behavior of the processor and ensure it operates as expected.

4. Modify and Extend:

   • You can modify the processor's design or add new instructions by editing the appropriate Verilog files.

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Contributing

Contributions to the project are welcome! If you have suggestions, bug reports, or wish to add new features, please follow these steps:

1. Fork the repository.
2. Create a new branch for your feature or bug fix.
3. Commit your changes and push them to your fork.
4. Submit a pull request describing your changes.

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License

This project is licensed under the MIT License. You are free to use, modify, and distribute this software as long as proper credit is given to the original author.

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Contact

For questions, suggestions, or any other inquiries, please contact Akor Michael at [email protected]. You can also open an issue on the project's GitHub page.

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Happy Assembly Coding!