A7-A11 SoC support

Makefile

@@ -101,10 +101,14 @@ OBJECTS := \
 	chickens.o \
 	chickens_avalanche.o \
 	chickens_blizzard.o \
+	chickens_cyclone_typhoon.o \
 	chickens_everest.o \
 	chickens_firestorm.o \
+	chickens_hurricane_zephyr.o \
+	chickens_monsoon_mistral.o \
 	chickens_icestorm.o \
 	chickens_sawtooth.o \
+	chickens_twister.o \
 	clk.o \
 	cpufreq.o \
 	dapf.o \

config.h

@@ -20,6 +20,8 @@
 
 // Target for device-specific debug builds
 //#define TARGET T8103
+// Some devices like Apple TV HD use other uarts for debug console
+//#define TARGET_BOARD 0x34
 
 #ifdef RELEASE
 # define FB_SILENT_MODE

m1n1-raw.ld

@@ -1,6 +1,7 @@
 ENTRY(_start)
 
 _stack_size = 0x20000;
+_stack_size_el3 = 0x8000;
 
 /* We are actually relocatable */
 . = 0;
@@ -71,6 +72,12 @@ SECTIONS {
         *(COMMON)
         _bss_end = .;
     } : data
+    .stack_el3 : ALIGN(0x4000) {
+        PROVIDE(_stack_top_el3 = .);
+        . += _stack_size_el3 - 8;
+        QUAD(0x5176694b43415453);
+        PROVIDE(_stack_bot_el3 = .);
+    }
     .stack : ALIGN(0x4000) {
         PROVIDE(_stack_top = .);
         . += _stack_size - 8;

m1n1.ld

@@ -4,6 +4,7 @@ ENTRY(_start)
 _va_base = 0xFFFFFE0007004000;
 
 _stack_size = 0x20000;
+_stack_size_el3 = 0x8000;
 
 _max_payload_size = 64*1024*1024;
 
@@ -176,6 +177,10 @@ SECTIONS {
         *(COMMON)
         . = ALIGN(0x4000);
         _bss_end = .;
+        PROVIDE(_stack_top_el3 = .);
+        . += _stack_size_el3;
+        PROVIDE(_stack_bot_el3 = .);
+        . = ALIGN(0x4000);
         PROVIDE(_stack_top = .);
         . += _stack_size;
         PROVIDE(_stack_bot = .);

proxyclient/m1n1/proxy.py

@@ -494,6 +494,7 @@ class M1N1Proxy(Reloadable):
     P_PUT_SIMD_STATE = 0x00f
     P_REBOOT = 0x010
     P_SLEEP = 0x011
+    P_EL3_CALL = 0x012
 
     P_WRITE64 = 0x100
     P_WRITE32 = 0x101
@@ -760,6 +761,10 @@ def reboot(self):
         self.request(self.P_REBOOT, no_reply=True)
     def sleep(self, deep=False):
         self.request(self.P_SLEEP, deep, no_reply=True)
+    def el3_call(self, addr, *args):
+        if len(args) > 4:
+            raise ValueError("Too many arguments")
+        return self.request(self.P_EL3_CALL, addr, *args)
 
     def write64(self, addr, data):
         '''write 8 byte value to given address'''

src/aic.c

@@ -147,6 +147,11 @@ void aic_set_sw(int irq, bool active)
                 MASK_BIT(irq));
 }
 
+void aic_write(u32 reg, u32 val)
+{
+    write32(aic->base + reg, val);
+}
+
 uint32_t aic_ack(void)
 {
     return read32(aic->base + aic->regs.event);

src/aic.h

@@ -35,6 +35,7 @@ extern struct aic *aic;
 
 void aic_init(void);
 void aic_set_sw(int irq, bool active);
+void aic_write(u32 reg, u32 val);
 uint32_t aic_ack(void);
 
 #endif

src/arm_cpu_regs.h

@@ -309,6 +309,7 @@
 #define TCR_IPS_16TB   0b100UL
 #define TCR_TG1        GENMASK(31, 30)
 #define TCR_TG1_16K    0b01UL
+#define TCR_TG1_4K     0b10UL
 #define TCR_SH1        GENMASK(29, 28)
 #define TCR_SH1_IS     0b11UL
 #define TCR_ORGN1      GENMASK(27, 26)
@@ -321,6 +322,7 @@
 #define TCR_T1SZ_48BIT 16UL
 #define TCR_TG0        GENMASK(15, 14)
 #define TCR_TG0_16K    0b10UL
+#define TCR_TG0_4K     0b0UL
 #define TCR_SH0        GENMASK(13, 12)
 #define TCR_SH0_IS     0b11UL
 #define TCR_ORGN0      GENMASK(11, 10)

src/chickens.c

@@ -6,29 +6,56 @@
 #include "utils.h"
 
 /* Part IDs in MIDR_EL1 */
-#define MIDR_PART_T8181_ICESTORM  0x20
-#define MIDR_PART_T8181_FIRESTORM 0x21
-#define MIDR_PART_T8103_ICESTORM  0x22
-#define MIDR_PART_T8103_FIRESTORM 0x23
-#define MIDR_PART_T6000_ICESTORM  0x24
-#define MIDR_PART_T6000_FIRESTORM 0x25
-#define MIDR_PART_T6001_ICESTORM  0x28
-#define MIDR_PART_T6001_FIRESTORM 0x29
-#define MIDR_PART_T8110_BLIZZARD  0x30
-#define MIDR_PART_T8110_AVALANCHE 0x31
-#define MIDR_PART_T8112_BLIZZARD  0x32
-#define MIDR_PART_T8112_AVALANCHE 0x33
-#define MIDR_PART_T6020_BLIZZARD  0x34
-#define MIDR_PART_T6020_AVALANCHE 0x35
-#define MIDR_PART_T6021_BLIZZARD  0x38
-#define MIDR_PART_T6021_AVALANCHE 0x39
-#define MIDR_PART_T6031_EVEREST   0x49
-#define MIDR_PART_T6031_SAWTOOTH  0x48
+#define MIDR_PART_S5L8960X_CYCLONE  0x1
+#define MIDR_PART_T7000_TYPHOON     0x2
+#define MIDR_PART_T7001_TYPHOON     0x3
+#define MIDR_PART_S8000_TWISTER     0x4
+#define MIDR_PART_S8001_3_TWISTER   0x5
+#define MIDR_PART_T8010_2_HURRICANE 0x6
+#define MIDR_PART_T8011_HURRICANE   0x7
+#define MIDR_PART_T8015_MONSOON     0x8
+#define MIDR_PART_T8015_MISTRAL     0x9
+#define MIDR_PART_T8020_VORTEX      0xb
+#define MIDR_PART_T8020_TEMPSET     0xc
+#define MIDR_PART_T8006_TEMPSET     0xf
+#define MIDR_PART_T8027_VORTEX      0x10
+#define MIDR_PART_T8027_TEMPSET     0x11
+#define MIDR_PART_T8030_LIGHTNING   0x12
+#define MIDR_PART_T8030_THUNDER     0x13
+#define MIDR_PART_T8101_ICESTORM    0x20
+#define MIDR_PART_T8101_FIRESTORM   0x21
+#define MIDR_PART_T8103_ICESTORM    0x22
+#define MIDR_PART_T8103_FIRESTORM   0x23
+#define MIDR_PART_T6000_ICESTORM    0x24
+#define MIDR_PART_T6000_FIRESTORM   0x25
+#define MIDR_PART_T8301_THUNDER     0x26
+#define MIDR_PART_T6001_ICESTORM    0x28
+#define MIDR_PART_T6001_FIRESTORM   0x29
+#define MIDR_PART_T8110_BLIZZARD    0x30
+#define MIDR_PART_T8110_AVALANCHE   0x31
+#define MIDR_PART_T8112_BLIZZARD    0x32
+#define MIDR_PART_T8112_AVALANCHE   0x33
+#define MIDR_PART_T6020_BLIZZARD    0x34
+#define MIDR_PART_T6020_AVALANCHE   0x35
+#define MIDR_PART_T6021_BLIZZARD    0x38
+#define MIDR_PART_T6021_AVALANCHE   0x39
+#define MIDR_PART_T6031_EVEREST     0x49
+#define MIDR_PART_T6031_SAWTOOTH    0x48
 
 #define MIDR_REV_LOW  GENMASK(3, 0)
 #define MIDR_PART     GENMASK(15, 4)
 #define MIDR_REV_HIGH GENMASK(23, 20)
 
+void init_s5l8960x_cyclone(void);
+void init_t7000_typhoon(void);
+void init_t7001_typhoon(void);
+void init_samsung_twister(int rev);
+void init_tsmc_twister(void);
+void init_t8010_2_hurricane_zephyr(void);
+void init_t8011_hurricane_zephyr(void);
+void init_t8015_monsoon(void);
+void init_t8015_mistral(void);
+void init_t8015_monsoon(void);
 void init_m1_icestorm(void);
 void init_t8103_firestorm(int rev);
 void init_t6000_firestorm(int rev);
@@ -42,7 +69,8 @@ void init_t6021_avalanche(int rev);
 void init_t6031_sawtooth(void);
 void init_t6031_everest(int rev);
 
-bool cpufeat_actlr_el2;
+bool cpufeat_actlr_el2, cpufeat_fast_ipi, cpufeat_mmu_sprr;
+bool cpufeat_global_sleep, cpufeat_workaround_cyclone_cache;
 
 const char *init_cpu(void)
 {
@@ -56,19 +84,66 @@ const char *init_cpu(void)
     else
         reg_set(SYS_IMP_APL_HID4, HID4_DISABLE_DC_MVA | HID4_DISABLE_DC_SW_L2_OPS);
 
-    /* Enable NEX powergating, the reset cycles might be overriden by chickens */
-    if (!is_ecore()) {
-        reg_mask(SYS_IMP_APL_HID13, HID13_RESET_CYCLES_MASK, HID13_RESET_CYCLES(12));
-        reg_set(SYS_IMP_APL_HID14, HID14_ENABLE_NEX_POWER_GATING);
-    }
-
     uint64_t midr = mrs(MIDR_EL1);
     int part = FIELD_GET(MIDR_PART, midr);
     int rev = (FIELD_GET(MIDR_REV_HIGH, midr) << 4) | FIELD_GET(MIDR_REV_LOW, midr);
 
     printf("  CPU part: 0x%x rev: 0x%x\n", part, rev);
 
+    if (part >= MIDR_PART_T8015_MONSOON) {
+        /* Enable NEX powergating, the reset cycles might be overriden by chickens */
+        if (!is_ecore()) {
+            reg_mask(SYS_IMP_APL_HID13, HID13_RESET_CYCLES_MASK, HID13_RESET_CYCLES(12));
+            reg_set(SYS_IMP_APL_HID14, HID14_ENABLE_NEX_POWER_GATING);
+        }
+    }
+
     switch (part) {
+        case MIDR_PART_S5L8960X_CYCLONE:
+            cpu = "A7 Cyclone";
+            init_s5l8960x_cyclone();
+            break;
+
+        case MIDR_PART_T7000_TYPHOON:
+            cpu = "A8 Typhoon";
+            init_t7000_typhoon();
+            break;
+
+        case MIDR_PART_T7001_TYPHOON:
+            cpu = "A8X Typhoon";
+            init_t7001_typhoon();
+            break;
+
+        case MIDR_PART_S8000_TWISTER:
+            cpu = "A9 Twister (Samsung)";
+            init_samsung_twister(rev);
+            break;
+
+        case MIDR_PART_S8001_3_TWISTER:
+            cpu = "A9(X) Twister (TSMC)";
+            init_tsmc_twister();
+            break;
+
+        case MIDR_PART_T8010_2_HURRICANE:
+            cpu = "A10/T2 Hurricane-Zephyr";
+            init_t8010_2_hurricane_zephyr();
+            break;
+
+        case MIDR_PART_T8011_HURRICANE:
+            cpu = "A10X Hurricane-Zephyr";
+            init_t8011_hurricane_zephyr();
+            break;
+
+        case MIDR_PART_T8015_MONSOON:
+            cpu = "A11 Monsoon";
+            init_t8015_monsoon();
+            break;
+
+        case MIDR_PART_T8015_MISTRAL:
+            cpu = "A11 Mistral";
+            init_t8015_mistral();
+            break;
+
         case MIDR_PART_T8103_FIRESTORM:
             cpu = "M1 Firestorm";
             init_t8103_firestorm(rev);
@@ -147,23 +222,40 @@ const char *init_cpu(void)
     if (part >= MIDR_PART_T8110_BLIZZARD)
         cpufeat_actlr_el2 = true;
 
-    int core = mrs(MPIDR_EL1) & 0xff;
+    if (part >= MIDR_PART_T8101_ICESTORM && part != MIDR_PART_T8301_THUNDER) {
+        int core = mrs(MPIDR_EL1) & 0xff;
+
+        // Enable IRQs (at least necessary on t600x)
+        // XXX 0 causes pathological behavior in EL1, 2 works.
+        msr(SYS_IMP_APL_SIQ_CFG_EL1, 2);
+        sysop("isb");
+
+        msr(SYS_IMP_APL_AMX_CTX_EL1, core);
 
-    msr(SYS_IMP_APL_AMX_CTX_EL1, core);
-    msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
+        /* T8030 SPRR is different */
+        cpufeat_mmu_sprr = true;
+    }
+
+    if (part >= MIDR_PART_T8030_LIGHTNING)
+        msr(SYS_IMP_APL_AMX_CTL_EL1, 0x100);
 
-    // Enable IRQs (at least necessary on t600x)
-    // XXX 0 causes pathological behavior in EL1, 2 works.
-    msr(SYS_IMP_APL_SIQ_CFG_EL1, 2);
+    if (part >= MIDR_PART_T8015_MONSOON)
+        cpufeat_fast_ipi = true;
 
-    sysop("isb");
+    if (part >= MIDR_PART_T8010_2_HURRICANE)
+        cpufeat_global_sleep = true;
+    else {
+        /* Disable deep sleep */
+        reg_clr(SYS_IMP_APL_ACC_CFG, ACC_CFG_DEEP_SLEEP);
+        cpufeat_workaround_cyclone_cache = true;
+    }
 
     /* Unmask external IRQs, set WFI mode to up (2) */
     reg_mask(SYS_IMP_APL_CYC_OVRD,
              CYC_OVRD_FIQ_MODE_MASK | CYC_OVRD_IRQ_MODE_MASK | CYC_OVRD_WFI_MODE_MASK,
              CYC_OVRD_FIQ_MODE(0) | CYC_OVRD_IRQ_MODE(0) | CYC_OVRD_WFI_MODE(2));
 
-    /* Enable branch prediction state retention across ACC sleep */
+    // Enable branch prediction state retention across ACC sleep
     reg_mask(SYS_IMP_APL_ACC_CFG, ACC_CFG_BP_SLEEP_MASK, ACC_CFG_BP_SLEEP(3));
 
     return cpu;

src/chickens_cyclone_typhoon.c

@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: MIT */
+
+#include "cpu_regs.h"
+#include "utils.h"
+
+// This file includes chickens for both cyclone and typhoon chips
+// due to their similarity.
+
+static void init_common_cyclone_typhoon(void)
+{
+    /* "Disable LSP flush with context switch to work around bug in LSP
+            that can cause Cyclone to wedge when CONTEXTIDR is written." */
+    reg_set(SYS_IMP_APL_HID0, HID0_LOOP_BUFFER_DISABLE);
+
+    /* Not sure on what's happening here... did the meaning of this bit
+       change at some point? Original name: ARM64_REG_HID1_rccDisStallInactiveIexCtl */
+    reg_set(SYS_IMP_APL_HID1, HID1_DIS_SPEC_MDSB_INVL_ROB_FLUSH);
+    reg_set(SYS_IMP_APL_HID3, HID3_DIS_XMON_SNP_EVICT_TRIGGER_L2_STARAVTION_MODE);
+
+    reg_clr(SYS_IMP_APL_HID5, HID5_DIS_HWP_LD | HID5_DIS_HWP_ST);
+
+    // Change memcache data ID from 0 to 15
+    reg_set(SYS_IMP_APL_HID8, HID8_DATA_SET_ID0_VALUE(0xf) | HID8_DATA_SET_ID1_VALUE(0xf));
+}
+
+void init_t7000_typhoon(void)
+{
+    init_common_cyclone_typhoon();
+}
+
+void init_t7001_typhoon(void)
+{
+    init_common_cyclone_typhoon();
+
+    // Change memcache data ID from 0 to 15
+    reg_set(SYS_IMP_APL_HID8, HID8_DATA_SET_ID2_VALUE(0xf));
+}
+
+void init_s5l8960x_cyclone(void)
+{
+    init_common_cyclone_typhoon();
+    reg_set(SYS_IMP_APL_HID1, HID1_DIS_LSP_FLUSH_WITH_CONTEXT_SWITCH);
+}