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QuestaSim

amiilka edited this page Dec 14, 2021 · 7 revisions

Most common errors

  • Comma missing at the end of a line.
  • Entities names spelt incorrectly.
  • There are special symbols in your file path (e. g.: é, î, …).
  • The file that you are trying to compile is not in your project.

Bug: One or several signals are missing in the objects tab

Go to Simulate > Start simulation > Optimization options then select apply full visibility to all modules in the visibility tab

If you have the error "Error loading design"

Go to Simulate > Start simulation then select enable optimization

If the error still persists, it probably comes from an error in the names of your entities, architectures, components or signals. You should check that:

  1. You don't have two entities with the same names in the same project.
  2. When declaring a component in a high-level system (for example a test bench), the component name should be the same that the corresponding sub-system’s entity. The port definitions of the component must also match the port definitions of the sub-system’s entity exactly.

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