VHDL

How to do type conversion or casting in VHDL

The picture below illustrates how to convert between the most common VHDL types.

These functions are part of the numeric_std library.

(picture found at https://www.bitweenie.com/listings/vhdl-type-conversion/)

How to make a hierarchical design?

In VHDL it is advisable to use a divide and conquer approach. The pictures and the code below show how to make a hierarchical design composed out of two identical sub-modules.

The architecture of the TopLevel module should be:

What is the syntax for entity declaration?

Where :

• e_name is the name of the entity
• g_list is the list of design constants
• p_list is the list of design pins Instead of end entity, it is possible to write end {e_name}

When should I use component declaration?

A component is a term used for a VHDL sub-system that is instantiated within a higher-level system. It must be declared in the higher-level architecture system before the begin statement. A component only needs to be declared once. It can then be used as many times as necessary in the higher-level system architecture after the begin statement.

/!\The port definitions of the component must match the port definitions of the sub-system’s entity exactly.

Which VHDL constructions must be used inside a process?

Concurent constructions in VHDL

Concurrent constructions correspond to combinatorial logic, and should not be used inside processes.

• When-else
• With select

Sequential Constructions

These constructions correspond to sequential logic and should be used inside processes.

• If-then
• Case-is
• For loop