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Merge branch 'isa_fix_uvm' into 'devel'
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Isa fix uvm

See merge request ndk/ndk-app-minimal!59
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@jakubcabal
jakubcabal committed Jun 17, 2024
2 parents 62cc6fb + 5598f12 commit a1f2cf8
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Showing 5 changed files with 47 additions and 105 deletions.
11 changes: 7 additions & 4 deletions app/uvm/testbench.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -46,15 +46,15 @@ module testbench;
reset_if reset_user_x2(CLK_USER_X2);
reset_if reset_user_x3(CLK_USER_X3);
reset_if reset_user_x4(CLK_USER_X4);
// OUTPUT INTERFACE
// OUTPUT INTERFACE
reset_if reset_mi(MI_CLK);
reset_if reset_dma_x1(DMA_CLK_X1);
reset_if reset_dma_x2(DMA_CLK_X2);
reset_if reset_app(APP_CLK);
reset_if reset_mem[test_pkg::MEM_PORTS](MEM_CLK);

// ETHERNET I/O INTERFACE
mvb_if #(test_pkg::REGIONS, test_pkg::ETH_RX_HDR_WIDTH) eth_rx_mvb[test_pkg::ETH_STREAMS](APP_CLK);
mvb_if #(test_pkg::REGIONS, test_pkg::ETH_RX_HDR_WIDTH) eth_rx_mvb[test_pkg::ETH_STREAMS](APP_CLK);
mfb_if #(test_pkg::REGIONS, test_pkg::MFB_REG_SIZE, test_pkg::MFB_BLOCK_SIZE, test_pkg::MFB_ITEM_WIDTH, 0) eth_rx_mfb[test_pkg::ETH_STREAMS](APP_CLK);
mfb_if #(test_pkg::REGIONS, test_pkg::MFB_REG_SIZE, test_pkg::MFB_BLOCK_SIZE, test_pkg::MFB_ITEM_WIDTH, test_pkg::ETH_TX_HDR_WIDTH) eth_tx_mfb[test_pkg::ETH_STREAMS](APP_CLK);
// DMA I/O INTERFACE
Expand Down Expand Up @@ -108,6 +108,7 @@ module testbench;
// ETH
/////////////////////////
// ETH RX
// std_logic_vector(ETH_STREAMS* ETH_MFB_REGIONS*ETH_RX_HDR_WIDTH-1 downto 0);
logic [test_pkg::ETH_STREAMS*test_pkg::REGIONS*test_pkg::ETH_RX_HDR_WIDTH-1:0] eth_rx_mvb_data;
logic [test_pkg::ETH_STREAMS*test_pkg::REGIONS-1:0] eth_rx_mvb_vld;
logic [test_pkg::ETH_STREAMS-1:0] eth_rx_mvb_dst_rdy;
Expand Down Expand Up @@ -228,17 +229,19 @@ module testbench;


APPLICATION_CORE #(
.ETH_MFB_REGIONS (test_pkg::REGIONS),
.ETH_MFB_REG_SIZE (test_pkg::MFB_REG_SIZE),
.ETH_CHANNELS (test_pkg::ETH_CHANNELS),
.ETH_STREAMS (test_pkg::ETH_STREAMS),
.PCIE_ENDPOINTS (test_pkg::PCIE_ENDPOINTS),
.DMA_MFB_REGIONS (test_pkg::REGIONS),
.DMA_MFB_REG_SIZE (test_pkg::MFB_REG_SIZE),
.DMA_STREAMS (test_pkg::DMA_STREAMS),
.DMA_RX_CHANNELS (test_pkg::DMA_RX_CHANNELS),
.DMA_TX_CHANNELS (test_pkg::DMA_TX_CHANNELS),
.DMA_HDR_META_WIDTH(test_pkg::DMA_HDR_META_WIDTH),
.DMA_RX_FRAME_SIZE_MAX (test_pkg::DMA_PKT_MTU),
.DMA_TX_FRAME_SIZE_MAX (test_pkg::DMA_PKT_MTU),
.MFB_REGIONS (test_pkg::REGIONS),
.MFB_REG_SIZE (test_pkg::MFB_REG_SIZE),
.MFB_BLOCK_SIZE (test_pkg::MFB_BLOCK_SIZE),
.MFB_ITEM_WIDTH (test_pkg::MFB_ITEM_WIDTH),
.MEM_PORTS (test_pkg::MEM_PORTS),
Expand Down
31 changes: 6 additions & 25 deletions app/uvm/tests/base.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,6 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
uvm_app_core_minimal::env #(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR_WIDTH, DMA_STREAMS, DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_HDR_META_WIDTH, DMA_PKT_MTU,
REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MEM_PORTS, MEM_ADDR_WIDTH, MEM_BURST_WIDTH, MEM_DATA_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH) m_env;

bit timeout;
logic event_reset;
logic event_eth_rx_end[ETH_STREAMS];
logic event_dma_rx_end[DMA_STREAMS];
Expand Down Expand Up @@ -94,7 +93,6 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
mvb_seq.init_sequence();
mvb_seq.min_random_count = 50;
mvb_seq.max_random_count = 150;
mvb_seq.init_sequence();

forever begin
//mvb_seq.set_starting_phase(phase);
Expand All @@ -104,13 +102,12 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
endtask

task run_eth_meta(uvm_logic_vector_array::sequencer#(MFB_ITEM_WIDTH) sqr);
uvm_app_core_top_agent::logic_vector_sequence_lib_eth#(MFB_ITEM_WIDTH, ETH_RX_HDR_WIDTH) mvb_seq;
uvm_app_core_top_agent::logic_vector_sequence_lib_eth#(MFB_ITEM_WIDTH, ETH_RX_HDR_WIDTH) mvb_seq;

mvb_seq = uvm_app_core_top_agent::logic_vector_sequence_lib_eth#(MFB_ITEM_WIDTH, ETH_RX_HDR_WIDTH)::type_id::create("mvb_seq", this);
mvb_seq.init_sequence();
mvb_seq.min_random_count = 50;
mvb_seq.max_random_count = 150;
mvb_seq.init_sequence();

forever begin
//mvb_seq.set_starting_phase(phase);
Expand Down Expand Up @@ -224,17 +221,6 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
event_dma_rx_end[index] = 1'b0;
endtask

task test_wait_timeout(int unsigned time_length);
#(time_length*1us);
endtask

task test_wait_result();
do begin
#(600ns);
end while (m_env.m_scoreboard.used() != 0);
timeout = 0;
endtask

virtual task run_reset(uvm_phase phase);
uvm_reset::sequence_reset reset;
uvm_reset::sequence_run run;
Expand Down Expand Up @@ -272,6 +258,7 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
endtask

virtual task run_phase(uvm_phase phase);
time end_time;
run_packet_subsequences();

phase.raise_objection(this);
Expand Down Expand Up @@ -342,20 +329,14 @@ class base#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR
end
end


timeout = 1;
fork
test_wait_timeout(20);
test_wait_result();
join_any;

end_time = $time() + 20us;
while (end_time > $time() && m_env.m_scoreboard.used() != 0) begin
#(500ns);
end
phase.drop_objection(this);
endtask

function void report_phase(uvm_phase phase);
`uvm_info(this.get_full_name(), {"\n\tTEST : ", this.get_type_name(), " END\n"}, UVM_NONE);
if (timeout) begin
`uvm_error(this.get_full_name(), "\n\t===================================================\n\tTIMEOUT SOME PACKET STUCK IN DESIGN\n\t===================================================\n\n");
end
endfunction
endclass
94 changes: 26 additions & 68 deletions app/uvm/tests/full_speed.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -8,59 +8,6 @@
* SPDX-License-Identifier: BSD-3-Clause
*/

class mfb_rx_speed#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH) extends uvm_logic_vector_array_mfb::sequence_lib_rx#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH);
`uvm_object_param_utils( test::mfb_rx_speed#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH))
`uvm_sequence_library_utils(test::mfb_rx_speed#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH))

function new(string name = "mfb_rx_speed");
super.new(name);
init_sequence_library();
endfunction

virtual function void init_sequence(uvm_logic_vector_array_mfb::config_sequence param_cfg = null);
if (param_cfg == null) begin
this.cfg = new();
end else begin
this.cfg = param_cfg;
end
this.add_sequence(uvm_logic_vector_array_mfb::sequence_full_speed_rx #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH)::get_type());
this.add_sequence(uvm_logic_vector_array_mfb::sequence_stop_rx #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH)::get_type());
endfunction
endclass

class mfb_lib_tx#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH) extends uvm_sequence_library#(uvm_mfb::sequence_item #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH));
`uvm_object_param_utils( test::mfb_lib_tx#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH))
`uvm_sequence_library_utils(test::mfb_lib_tx#(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH))

function new(string name = "");
super.new(name);
init_sequence_library();
endfunction

// subclass can redefine and change run sequences
// can be useful in specific tests
virtual function void init_sequence();
this.add_sequence(uvm_mfb::sequence_full_speed_tx #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH)::get_type());
this.add_sequence(uvm_mfb::sequence_stop_tx #(REGIONS, REGION_SIZE, BLOCK_SIZE, ITEM_WIDTH, META_WIDTH)::get_type());
endfunction
endclass

class mvb_lib_tx#(ITEMS, ITEM_WIDTH) extends uvm_sequence_library#(uvm_mvb::sequence_item#(ITEMS, ITEM_WIDTH));
`uvm_object_param_utils( test::mvb_lib_tx#(ITEMS, ITEM_WIDTH))
`uvm_sequence_library_utils(test::mvb_lib_tx#(ITEMS, ITEM_WIDTH))

function new(string name = "");
super.new(name);
init_sequence_library();
endfunction

// subclass can redefine and change run sequences
// can be useful in specific tests
virtual function void init_sequence();
this.add_sequence(uvm_mvb::sequence_full_speed_tx#(ITEMS, ITEM_WIDTH)::get_type());
this.add_sequence(uvm_mvb::sequence_stop_tx#(ITEMS, ITEM_WIDTH)::get_type());
endfunction
endclass

class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_TX_HDR_WIDTH, DMA_STREAMS, DMA_RX_CHANNELS, DMA_TX_CHANNELS, DMA_HDR_META_WIDTH, DMA_PKT_MTU,
REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, MEM_PORTS, MEM_ADDR_WIDTH, MEM_BURST_WIDTH, MEM_DATA_WIDTH, MI_DATA_WIDTH, MI_ADDR_WIDTH) extends
Expand All @@ -77,16 +24,23 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_
string it_num;
it_num.itoa(it);

uvm_logic_vector_array_mfb::sequence_lib_rx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::set_inst_override(mfb_rx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::get_type(),
uvm_logic_vector_array_mfb::sequence_lib_rx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::set_inst_override(uvm_logic_vector_array_mfb::sequence_lib_rx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::get_type(),
{this.get_full_name(), ".m_env.m_eth_mfb_rx_", it_num ,".*"});

uvm_logic_vector_mvb::sequence_lib_rx#(REGIONS, ETH_RX_HDR_WIDTH)::type_id::set_inst_override(uvm_logic_vector_mvb::sequence_lib_speed_rx#(REGIONS, ETH_RX_HDR_WIDTH)::get_type(),
{this.get_full_name(), ".m_env.m_eth_mvb_rx_", it_num,".*"});
end

for (int unsigned it = 0; it < DMA_STREAMS; it++) begin
string it_num;
it_num.itoa(it);

uvm_logic_vector_array_mfb::sequence_lib_rx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::set_inst_override(mfb_rx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::get_type(),
uvm_logic_vector_array_mfb::sequence_lib_rx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::set_inst_override(uvm_logic_vector_array_mfb::sequence_lib_rx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::get_type(),
{this.get_full_name(), ".m_env.m_dma_mfb_rx_", it_num,".*"});

uvm_logic_vector_mvb::sequence_lib_rx#(REGIONS, DMA_RX_MVB_WIDTH)::type_id::set_inst_override(uvm_logic_vector_mvb::sequence_lib_speed_rx#(REGIONS, DMA_RX_MVB_WIDTH)::get_type(),
{this.get_full_name(), ".m_env.m_dma_mvb_rx_", it_num,".*"});

//.mfb_seq
end

Expand All @@ -95,7 +49,7 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_

function void connect_phase(uvm_phase phase);
super.connect_phase(phase);
m_env.delay_max_set(200ns);
m_env.delay_max_set(1ms);
endfunction

static function type_id get_type();
Expand All @@ -111,9 +65,9 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_
endfunction

virtual task eth_tx_sequence(uvm_phase phase, int unsigned index);
mfb_lib_tx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, ETH_TX_HDR_WIDTH) mfb_seq;
uvm_mfb::sequence_lib_tx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, ETH_TX_HDR_WIDTH) mfb_seq;

mfb_seq = mfb_lib_tx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, ETH_TX_HDR_WIDTH)::type_id::create("mfb_eth_tx_seq", this);
mfb_seq = uvm_mfb::sequence_lib_tx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, ETH_TX_HDR_WIDTH)::type_id::create("mfb_eth_tx_seq", this);
mfb_seq.init_sequence();
mfb_seq.min_random_count = 10;
mfb_seq.max_random_count = 20;
Expand All @@ -136,21 +90,23 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_

//SEND PACKETS
//mfb_seq.set_starting_phase(phase);
assert(mfb_seq.randomize());
mfb_seq.start(m_eth_agent[index].m_sequencer);
event_eth_rx_end[index] = 1'b1;
for (int unsigned it = 0; it < 4; it++) begin
assert(mfb_seq.randomize());
mfb_seq.start(m_eth_agent[index].m_sequencer);
end
event_eth_rx_end[index] = 1'b0;
endtask

virtual task dma_tx_sequence(uvm_phase phase, int unsigned index);
mfb_lib_tx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0) mfb_seq;
mvb_lib_tx#(REGIONS, DMA_TX_MVB_WIDTH) mvb_seq;
uvm_mfb::sequence_lib_tx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0) mfb_seq;
uvm_mvb::sequence_lib_tx_speed#(REGIONS, DMA_TX_MVB_WIDTH) mvb_seq;

mfb_seq = mfb_lib_tx#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::create("mfb_dma_tx_seq", this);
mfb_seq = uvm_mfb::sequence_lib_tx_speed#(REGIONS, MFB_REG_SIZE, MFB_BLOCK_SIZE, MFB_ITEM_WIDTH, 0)::type_id::create("mfb_dma_tx_seq", this);
mfb_seq.init_sequence();
mfb_seq.min_random_count = 10;
mfb_seq.max_random_count = 20;

mvb_seq = mvb_lib_tx#(REGIONS, DMA_TX_MVB_WIDTH)::type_id::create("mvb_dma_tx_seq", this);
mvb_seq = uvm_mvb::sequence_lib_tx_speed#(REGIONS, DMA_TX_MVB_WIDTH)::type_id::create("mvb_dma_tx_seq", this);
mvb_seq.init_sequence();
mvb_seq.min_random_count = 10;
mvb_seq.max_random_count = 20;
Expand Down Expand Up @@ -180,8 +136,10 @@ class full_speed#(ETH_STREAMS, ETH_CHANNELS, ETH_PKT_MTU, ETH_RX_HDR_WIDTH, ETH_

//SEND PACKETS
//mfb_seq.set_starting_phase(phase);
assert(mfb_seq.randomize());
mfb_seq.start(m_dma_agent[index].m_sequencer);
event_dma_rx_end[index] = 1'b1;
for (int unsigned it = 0; it < 4; it++) begin
assert(mfb_seq.randomize());
mfb_seq.start(m_dma_agent[index].m_sequencer);
end
event_dma_rx_end[index] = 1'b0;
endtask
endclass
8 changes: 0 additions & 8 deletions app/uvm/top_level.fdo
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,6 @@ set SIM_FLAGS(UVM_TEST) "test::base"
#set SIM_FLAGS(UVM_TEST) "test::full_speed"
#set SIM_FLAGS(UVM_VERBOSITY) "UVM_MEDIUM"
#set SIM_FLAGS(DEBUG) true
#set SIM_FLAGS(RAND_SEED) 1305311032
#set SIM_FLAGS(EXTRA_VFLAGS) "-voptargs=+acc"

# Global include file for compilation
source "$OFM_PATH/build/Modelsim.inc.fdo"
Expand All @@ -47,9 +45,3 @@ config wave -signalnamewidth 1
#run verification
nb_sim_run

# Reports
# Uncomment lines below to generate html coce coverage report
if {$SIM_FLAGS(CODE_COVERAGE)} {
coverage save -instance /testbench/DUT -code bcefst -verbose -testname {*}$TEST_NAME actual.ucdb
coverage report -html -output cov_html -instance=/testbench/DUT -source -details -assert -directive -cvg -code bcefst -verbose -threshL 50 -threshH 90
}
8 changes: 8 additions & 0 deletions app/uvm/ver_settings.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,6 +30,7 @@
"RESET_WIDTH" : 4,
"BOARD" : "\\\"400G1\\\"",
"DEVICE" : "\\\"ULTRASCALE\\\"",
"__core_params__" : {"UVM_TEST" : "test::base"},
},
"eth_1" : {
"ETH_PORTS" : 1,
Expand Down Expand Up @@ -60,11 +61,18 @@
"ETH_CHANNELS" : 1,
},

"test_speed" : {
"__core_params__" : {"UVM_TEST" : "test::full_speed"},
}



"_combinations_" : (
("default",), # Works the same as '("default",),' as the "default" is applied in every combination
("default", "test_speed", ),
("eth_1", "dma_1", "mfb",),
("dma_1", "eth_ch1", "mfb_1",),
("dma_1", "eth_ch1",),
("eth_1", "dma_1", "mfb", "test_speed", ),
),
}

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