Merge branch 'benesd_feat_iwave_final' into 'devel'

feat(cards): add support for iwave g35p accelerator card

See merge request ndk/ndk-fpga!117

apps/minimal/build/g35p/Makefile

@@ -0,0 +1,27 @@
+# Makefile: Makefile for iWave G35P Accelerator Card
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+
+# NOTE: Usage of the configuration parameters in this file is described
+# in the Parametrization section of the NDK-CORE documentation.
+
+# Set path to top-level of NDK-FPGA repository
+COMBO_BASE = ../../../..
+CARD_BASE = $(COMBO_BASE)/cards/iwave/g35p
+APP_CONF = app_conf.tcl
+OUTPUT_NAME = g35p-minimal
+
+.PHONY: all 100g2
+
+all: 100g2
+
+100g2: ETH_PORTS=2
+100g2: ETH_PORT_SPEED=100
+100g2: ETH_PORT_CHAN=1
+100g2: OUTPUT_NAME:=g35p-minimal-100g2
+100g2: build
+
+include $(CARD_BASE)/src/card.mk

apps/minimal/build/g35p/Vivado.tcl

@@ -0,0 +1,32 @@
+# Vivado.tcl: Vivado tcl script to compile whole FPGA design
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+
+# NOTE: The purpose of this file is described in the Parametrization section of
+# the NDK-CORE documentation.
+
+# ----- Setting basic synthesis options ---------------------------------------
+# Sourcing all configuration parameters
+source $env(CARD_BASE)/src/Vivado.inc.tcl
+
+# Create only a Vivado project for further design flow driven from Vivado GUI
+# "0" ... full design flow in command line
+# "1" ... project composition only for further dedesign flow in GUI
+set SYNTH_FLAGS(PROJ_ONLY) "0"
+
+# Associative array which is propagated to APPLICATION_CORE, add other
+# parameters if necessary.
+set APP_ARCHGRP(APP_CORE_ENABLE) $APP_CORE_ENABLE
+
+# Convert associative array to list
+set APP_ARCHGRP_L [array get APP_ARCHGRP]
+
+# ----- Add application core to main component list ---------------------------
+lappend HIERARCHY(COMPONENTS) \
+    [list "APPLICATION_CORE" "$OFM_PATH/apps/minimal/top" $APP_ARCHGRP_L]
+
+# Call main function which handle targets
+nb_main

apps/minimal/build/g35p/app_conf.tcl

@@ -0,0 +1,28 @@
+# app_conf.tcl: Application specific parameters which can be changed by the user
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+
+# NOTE: The detailed description of the usage of this file can be viewed in the
+# Parametrizing section of the NDK-CORE documentation.
+
+# NOTE: Use the PCIE_CONF make parameter to select the PCIe configuration.
+
+# ------------------------------------------------------------------------------
+# DMA parameters:
+# ------------------------------------------------------------------------------
+# The minimum number of RX/TX DMA channels for this card is 16.
+set DMA_RX_CHANNELS      16
+set DMA_TX_CHANNELS      16
+# In blocking mode, packets are dropped only when the RX DMA channel is off.
+# In non-blocking mode, packets are dropped whenever they cannot be sent.
+set DMA_RX_BLOCKING_MODE true
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set PROJECT_NAME "NDK_MINIMAL"
+set PROJECT_VARIANT "$ETH_PORT_SPEED(0)G$ETH_PORTS"
+set PROJECT_VERSION [exec cat ../../../../VERSION]

apps/minimal/tests/cocotb/top-level-sim.jenkinsfile

@@ -23,7 +23,7 @@ def common_card_test_run(CARD_NAME) {
     }
 }
 
-def CARDS = ["alveo-u200", "alveo-u55c", "vcu118", "ia-420f", "n6010", "fb2cghh", "fb4cgg3", "nfb-200g2ql", "dk-dev-1sdx-p"]
+def CARDS = ["alveo-u200", "alveo-u55c", "vcu118", "ia-420f", "n6010", "fb2cghh", "fb4cgg3", "nfb-200g2ql", "dk-dev-1sdx-p", "g35p"]
 
 node("preklad") {
     cleanWs()

cards/iwave/g35p/config/card_conf.tcl

@@ -0,0 +1,85 @@
+# card_conf.tcl: Default parameters for iWave G35P
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+
+# NOTE: For the detailed description of this file, visit the Parametrization section
+# in the documentation of the NDK-CORE repository.
+
+set PROJECT_NAME ""
+
+# ------------------------------------------------------------------------------
+# ETH parameters:
+# ------------------------------------------------------------------------------
+# Number of Ethernet ports, must match number of items in list ETH_PORTS_SPEED!
+# (with two QSFP). Set the correct number of ETH ports according to your card.
+set ETH_PORTS         $env(ETH_PORTS)
+# Speed for each one of the ETH_PORTS (allowed values: 100)
+# ETH_PORT_SPEED is an array where each index represents given ETH_PORT and
+# each index has associated a required port speed.
+# NOTE: at this moment, all ports must have same speed !
+set ETH_PORT_SPEED(0) $env(ETH_PORT_SPEED)
+set ETH_PORT_SPEED(1) $env(ETH_PORT_SPEED)
+
+# Number of channels for each one of the ETH_PORTS (allowed values: 1 for ETH_PORT_SPEED=100, 4 for ETH_PORT_SPEED<100)
+# ETH_PORT_CHAN is an array where each index represents given ETH_PORT and
+# each index has associated a required number of channels this port has.
+# NOTE: at this moment, all ports must have same number of channels !
+set ETH_PORT_CHAN(0) $env(ETH_PORT_CHAN)
+set ETH_PORT_CHAN(1) $env(ETH_PORT_CHAN)
+
+# Number of lanes for each one of the ETH_PORTS
+# Typical values: 4 (QSFP), 8 (QSFP-DD)
+set ETH_PORT_LANES(0) 8
+set ETH_PORT_LANES(1) 8
+
+# ------------------------------------------------------------------------------
+# PCIe parameters (not all combinations work):
+# ------------------------------------------------------------------------------
+# Supported combinations for this card:
+# 1x PCIe Gen3 x16  -- PCIE_ENDPOINT_MODE=0 (Note: default configuration)
+# ------------------------------------------------------------------------------
+
+# Set default PCIe configuration
+set PCIE_CONF "1xGen3x16"
+if { [info exist env(PCIE_CONF)] } {
+    set PCIE_CONF $env(PCIE_CONF)
+}
+
+# Parsing PCIE_CONF string to list of parameters
+set pcie_conf_list [ParsePcieConf $PCIE_CONF]
+
+# PCIe Generation:
+# 3 = PCIe Gen3
+set PCIE_GEN           [lindex $pcie_conf_list 1]
+# PCIe endpoints:
+# 1 = 1x PCIe x16 in one slot
+set PCIE_ENDPOINTS     [lindex $pcie_conf_list 0]
+# PCIe endpoint mode:
+# 0 = 1x16 lanes
+set PCIE_ENDPOINT_MODE [lindex $pcie_conf_list 2]
+
+# ------------------------------------------------------------------------------
+# DMA parameters:
+# ------------------------------------------------------------------------------
+# This variable can be set in COREs *.mk file or as a parameter when launching the make
+set DMA_TYPE             $env(DMA_TYPE)
+# The minimum number of RX/TX DMA channels for this card is 16.
+set DMA_RX_CHANNELS      16
+set DMA_TX_CHANNELS      16
+# In blocking mode, packets are dropped only when the RX DMA channel is off.
+# In non-blocking mode, packets are dropped whenever they cannot be sent.
+set DMA_RX_BLOCKING_MODE true
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set TSU_ENABLE true
+
+# ------------------------------------------------------------------------------
+# DDR4 parameters:
+# ------------------------------------------------------------------------------
+# External DDR4 memory settings.
+set MEM_PORTS 0

cards/iwave/g35p/config/card_const.tcl

@@ -0,0 +1,50 @@
+# card_const.tcl: Card specific parameters (developer only)
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+
+# WARNING: The user should not deliberately change parameters in this file. For
+# the description of this file, visit the Parametrization section in the
+# documentation of the NDK-CORE repostiory
+
+set CARD_NAME "IWAVE-G35P"
+# Achitecture of Clock generator
+set CLOCK_GEN_ARCH "USP"
+# Achitecture of PCIe module
+set PCIE_MOD_ARCH "USP"
+# Achitecture of SDM/SYSMON module
+# TODO: ZYNQ_ULTRASCALE
+set SDM_SYSMON_ARCH "EMPTY"
+# Boot controller type
+set BOOT_TYPE 0
+# Achitecture of Network module
+set NET_MOD_ARCH "CMAC"
+
+# Total number of QSFP cages
+set QSFP_CAGES       2
+# I2C address of each QSFP cage - There is no I2C connected to the QSFP cages (they are set to pull-up).
+set QSFP_I2C_ADDR(0) "0xA0"
+set QSFP_I2C_ADDR(1) "0xA0"
+
+# ------------------------------------------------------------------------------
+# Checking of parameter compatibility
+# ------------------------------------------------------------------------------
+
+if {!($PCIE_ENDPOINTS == 1 && $PCIE_GEN == 3 && $PCIE_ENDPOINT_MODE == 0) } {
+    error "Incompatible PCIe configuration: PCIE_ENDPOINTS = $PCIE_ENDPOINTS, PCIE_GEN = $PCIE_GEN, PCIE_ENDPOINT_MODE = $PCIE_ENDPOINT_MODE!
+Allowed PCIe configurations:
+- 1xGen3x16  -- PCIE_GEN=3, PCIE_ENDPOINTS=1, PCIE_ENDPOINT_MODE=0"
+}
+
+if {!($MEM_PORTS == 0) } {
+    error "Incompatible MEM_PORTS configuration: MEM_PORTS = $MEM_PORTS!
+Allowed MEM_PORTS configurations:
+- MEM_PORTS=0 -- External memory disabled, memory controllers are not instantiated."
+}
+
+# ------------------------------------------------------------------------------
+# Other parameters:
+# ------------------------------------------------------------------------------
+set TSU_FREQUENCY 322265625

cards/iwave/g35p/constr/general.xdc

@@ -0,0 +1,17 @@
+# general.xdc
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# Bitstream configuration
+set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN enable [current_design]
+set_property CONFIG_MODE B_SCAN [current_design]
+set_property BITSTREAM.CONFIG.OVERTEMPSHUTDOWN enable [current_design]
+
+# General pins
+set_property PACKAGE_PIN AT22 [get_ports SYSCLK]
+set_property IOSTANDARD DIFF_SSTL12 [get_ports SYSCLK]
+
+create_clock -period 3.333 -name sysclk [get_ports SYSCLK]

cards/iwave/g35p/constr/gty_loc.xdc

@@ -0,0 +1,21 @@
+# qsfp_loc.xdc
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+# ==============================================================================
+# LOC locations for CMAC interfaces
+# ==============================================================================
+
+set_property LOC CMACE4_X0Y0 [get_cells -hierarchical -filter {NAME =~ *eth_core_g[0].network_mod_core_i/cmac_eth_1x100g_i/* && REF_NAME==CMACE4}]
+set_property LOC GTYE4_CHANNEL_X0Y8 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[0]*" }]
+set_property LOC GTYE4_CHANNEL_X0Y9 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[1]*" }]
+set_property LOC GTYE4_CHANNEL_X0Y10 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[2]*" }]
+set_property LOC GTYE4_CHANNEL_X0Y11 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[0]*" && NAME =~ "*channel_inst[3]*" }]
+
+set_property LOC CMACE4_X0Y1 [get_cells -hierarchical -filter {NAME =~ *eth_core_g[1].network_mod_core_i/cmac_eth_1x100g_i/* && REF_NAME==CMACE4}]
+set_property LOC GTYE4_CHANNEL_X0Y16 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[0]*" }]
+set_property LOC GTYE4_CHANNEL_X0Y17 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[1]*" }]
+set_property LOC GTYE4_CHANNEL_X0Y18 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[2]*" }]
+set_property LOC GTYE4_CHANNEL_X0Y19 [get_cells -hierarchical -filter { PRIMITIVE_TYPE == ADVANCED.GT.GTYE4_CHANNEL && NAME =~ "*eth_core_g[1]*" && NAME =~ "*channel_inst[3]*" }]

cards/iwave/g35p/constr/pcie.xdc

@@ -0,0 +1,88 @@
+# pcie.xdc
+# Copyright (C) 2024 BrnoLogic, Ltd.
+# Author(s): David Beneš <[email protected]>
+#
+# SPDX-License-Identifier: BSD-3-Clause
+
+set_property PACKAGE_PIN AD12 [get_ports {PCIE_SYSCLK_P}]
+set_property PACKAGE_PIN AD11 [get_ports {PCIE_SYSCLK_N}]
+
+set_property PACKAGE_PIN D2 [get_ports {PCIE_SYSRST_N}]
+set_property IOSTANDARD LVCMOS33 [get_ports {PCIE_SYSRST_N}]
+
+create_clock -period 10.000 -name pcie_clk_p -waveform {0.000 5.000} [get_ports {PCIE_SYSCLK_P}]
+
+set_property PACKAGE_PIN AM4 [get_ports {PCIE_RX_P[0]}]
+set_property PACKAGE_PIN AL2 [get_ports {PCIE_RX_P[1]}]
+set_property PACKAGE_PIN AK4 [get_ports {PCIE_RX_P[2]}]
+set_property PACKAGE_PIN AJ2 [get_ports {PCIE_RX_P[3]}]
+set_property PACKAGE_PIN AH4 [get_ports {PCIE_RX_P[4]}]
+set_property PACKAGE_PIN AG2 [get_ports {PCIE_RX_P[5]}]
+set_property PACKAGE_PIN AF4 [get_ports {PCIE_RX_P[6]}]
+set_property PACKAGE_PIN AE2 [get_ports {PCIE_RX_P[7]}]
+set_property PACKAGE_PIN AD4 [get_ports {PCIE_RX_P[8]}]
+set_property PACKAGE_PIN AC2 [get_ports {PCIE_RX_P[9]}]
+set_property PACKAGE_PIN AB4 [get_ports {PCIE_RX_P[10]}]
+set_property PACKAGE_PIN AA2 [get_ports {PCIE_RX_P[11]}]
+set_property PACKAGE_PIN Y4 [get_ports {PCIE_RX_P[12]}]
+set_property PACKAGE_PIN W2 [get_ports {PCIE_RX_P[13]}]
+set_property PACKAGE_PIN V4 [get_ports {PCIE_RX_P[14]}]
+set_property PACKAGE_PIN U2 [get_ports {PCIE_RX_P[15]}]
+
+set_property PACKAGE_PIN AM3 [get_ports {PCIE_RX_N[0]}]
+set_property PACKAGE_PIN AL1 [get_ports {PCIE_RX_N[1]}]
+set_property PACKAGE_PIN AK3 [get_ports {PCIE_RX_N[2]}]
+set_property PACKAGE_PIN AJ1 [get_ports {PCIE_RX_N[3]}]
+set_property PACKAGE_PIN AH3 [get_ports {PCIE_RX_N[4]}]
+set_property PACKAGE_PIN AG1 [get_ports {PCIE_RX_N[5]}]
+set_property PACKAGE_PIN AF3 [get_ports {PCIE_RX_N[6]}]
+set_property PACKAGE_PIN AE1 [get_ports {PCIE_RX_N[7]}]
+set_property PACKAGE_PIN AD3 [get_ports {PCIE_RX_N[8]}]
+set_property PACKAGE_PIN AC1 [get_ports {PCIE_RX_N[9]}]
+set_property PACKAGE_PIN AB3 [get_ports {PCIE_RX_N[10]}]
+set_property PACKAGE_PIN AA1 [get_ports {PCIE_RX_N[11]}]
+set_property PACKAGE_PIN Y3 [get_ports {PCIE_RX_N[12]}]
+set_property PACKAGE_PIN W1 [get_ports {PCIE_RX_N[13]}]
+set_property PACKAGE_PIN V3 [get_ports {PCIE_RX_N[14]}]
+set_property PACKAGE_PIN U1 [get_ports {PCIE_RX_N[15]}]
+
+set_property PACKAGE_PIN AL6 [get_ports {PCIE_TX_P[0]}]
+set_property PACKAGE_PIN AK8 [get_ports {PCIE_TX_P[1]}]
+set_property PACKAGE_PIN AJ6 [get_ports {PCIE_TX_P[2]}]
+set_property PACKAGE_PIN AH8 [get_ports {PCIE_TX_P[3]}]
+set_property PACKAGE_PIN AG6 [get_ports {PCIE_TX_P[4]}]
+set_property PACKAGE_PIN AF8 [get_ports {PCIE_TX_P[5]}]
+set_property PACKAGE_PIN AE6 [get_ports {PCIE_TX_P[6]}]
+set_property PACKAGE_PIN AD8 [get_ports {PCIE_TX_P[7]}]
+set_property PACKAGE_PIN AC6 [get_ports {PCIE_TX_P[8]}]
+set_property PACKAGE_PIN AB8 [get_ports {PCIE_TX_P[9]}]
+set_property PACKAGE_PIN AA6 [get_ports {PCIE_TX_P[10]}]
+set_property PACKAGE_PIN Y8 [get_ports {PCIE_TX_P[11]}]
+set_property PACKAGE_PIN W6 [get_ports {PCIE_TX_P[12]}]
+set_property PACKAGE_PIN V8 [get_ports {PCIE_TX_P[13]}]
+set_property PACKAGE_PIN U6 [get_ports {PCIE_TX_P[14]}]
+set_property PACKAGE_PIN T8 [get_ports {PCIE_TX_P[15]}]
+
+set_property PACKAGE_PIN AL5 [get_ports {PCIE_TX_N[0]}]
+set_property PACKAGE_PIN AK7 [get_ports {PCIE_TX_N[1]}]
+set_property PACKAGE_PIN AJ5 [get_ports {PCIE_TX_N[2]}]
+set_property PACKAGE_PIN AH7 [get_ports {PCIE_TX_N[3]}]
+set_property PACKAGE_PIN AG5 [get_ports {PCIE_TX_N[4]}]
+set_property PACKAGE_PIN AF7 [get_ports {PCIE_TX_N[5]}]
+set_property PACKAGE_PIN AE5 [get_ports {PCIE_TX_N[6]}]
+set_property PACKAGE_PIN AD7 [get_ports {PCIE_TX_N[7]}]
+set_property PACKAGE_PIN AC5 [get_ports {PCIE_TX_N[8]}]
+set_property PACKAGE_PIN AB7 [get_ports {PCIE_TX_N[9]}]
+set_property PACKAGE_PIN AA5 [get_ports {PCIE_TX_N[10]}]
+set_property PACKAGE_PIN Y7 [get_ports {PCIE_TX_N[11]}]
+set_property PACKAGE_PIN W5 [get_ports {PCIE_TX_N[12]}]
+set_property PACKAGE_PIN V7 [get_ports {PCIE_TX_N[13]}]
+set_property PACKAGE_PIN U5 [get_ports {PCIE_TX_N[14]}]
+set_property PACKAGE_PIN T7 [get_ports {PCIE_TX_N[15]}]
+
+####################################################################################
+# Processing System Peripherals IO Constraints
+#####################################################################################
+
+# set_property PACKAGE_PIN B2 [get_ports PS_PCIE_RST]
+# set_property PACKAGE_PIN B1 [get_ports PS_PCIE_INT]