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Fpga support (#16)
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* getting all the source files for simulation

* Update uart_programmer.py

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Co-authored-by: Georgios Nikolaidis <[email protected]>
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George-RG and Georgios Nikolaidis authored Aug 15, 2024
1 parent a41eb84 commit 2f72e7f
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Showing 2 changed files with 22 additions and 10 deletions.
28 changes: 20 additions & 8 deletions cmake/fpga/uart_programmer/uart_programmer.py
Original file line number Diff line number Diff line change
Expand Up @@ -19,18 +19,30 @@ def program(
text_bytes = b''
for line in text_lines:
line = line.strip()
byte_data = bytes.fromhex(line)
byte_data = bytearray(byte_data)
byte_data.reverse()
text_bytes += byte_data

if line.startswith('@') or line == '':
continue

words = line.split()
for word in words:
byte_data = bytes.fromhex(word)
byte_data = bytearray(byte_data)
byte_data.reverse()
text_bytes += byte_data

data_bytes = b''
for line in data_lines:
line = line.strip()
byte_data = bytes.fromhex(line)
byte_data = bytearray(byte_data)
byte_data.reverse()
data_bytes += byte_data

if line.startswith('@') or line == '':
continue

words = line.split()
for word in words:
byte_data = bytes.fromhex(word)
byte_data = bytearray(byte_data)
byte_data.reverse()
data_bytes += byte_data

num_text_bytes = len(text_bytes).to_bytes(4, byteorder='little')
num_data_bytes = (len(data_bytes)).to_bytes(4, byteorder='little')
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4 changes: 2 additions & 2 deletions cmake/sim/verilator/verilate.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -71,8 +71,8 @@ function(verilate IP_LIB)
endforeach()

get_ip_rtl_sources(SOURCES ${IP_LIB})
# Where is defined V_SOURCES (or is it always empty)?
list(PREPEND SOURCES ${V_SOURCES})
get_ip_sim_only_sources(SIM_SOURCES ${IP_LIB})
list(PREPEND SOURCES ${SIM_SOURCES})

get_ip_sources(CFG_FILE ${IP_LIB} VERILATOR_CFG)
list(PREPEND SOURCES ${CFG_FILE})
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