fix docs

HEP-SoC · Dec 21, 2024 · 3883d33 · 3883d33
1 parent 5166025
commit 3883d33
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/docs/docs/examples/simulation.md b/docs/docs/examples/simulation.md
@@ -14,8 +14,8 @@ For this step make sure you have Iverilog and/or Verilator installed on your sys
 Lets create a simple verilog testbench file:
 
 import CodeBlock from '@theme/CodeBlock';
-export const tb_v = require('!!raw-loader!../../../examples/sim_example/tb.v')?.default;
-export const cmakelists = require('!!raw-loader!../../../examples/sim_example/CMakeLists.txt')?.default;
+export const tb_v = require('!!raw-loader!../../../examples/simple_verilog/tb.v')?.default;
+export const cmakelists = require('!!raw-loader!../../../examples/simple_verilog/CMakeLists.txt')?.default;
 
 ## tb.v