Refactor simulation examples

Provided:
    * simple_verilog - Simple verilog only testbench for all simulators
    * simple_mixed_language - Verilog and VHDL tb for all capable sims
    * Remove modelsim and vcs examples

examples/dpi-c/CMakeLists.txt

@@ -3,7 +3,10 @@ project(dpi_example NONE)
 
 include("../../SoCMakeConfig.cmake")
 
-option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;verilator" "modelsim")
+option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;vcs;verilator;all" "modelsim")
+if(SIMULATOR STREQUAL "all")
+    set(ALL_SIMS TRUE)
+endif()
 
 add_ip(tb
     DESCRIPTION "Simple verilog testbench"
@@ -17,17 +20,23 @@ add_subdirectory(hello)
 
 ip_link(${IP} hello_dpi)
 
-if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim")
+if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
     modelsim(${IP})
+endif()
 
-elseif(SIMULATOR STREQUAL "xcelium")
+if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS)
     xcelium(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS)
+    vcs(${IP})
+endif()
 
-elseif(SIMULATOR STREQUAL "verilator")
+if(SIMULATOR STREQUAL "verilator" OR ALL_SIMS)
     enable_language(CXX)
     verilator(${IP})
-    add_executable(main Vtb__main.cpp)
-    target_link_libraries(main tb__vlt)
+    add_executable(verilator_tb EXCLUDE_FROM_ALL Vtb__main.cpp )
+    target_link_libraries(verilator_tb tb__vlt)
 endif()
 
 help()

examples/dpi-c/hello/CMakeLists.txt

@@ -1,11 +1,13 @@
 cmake_minimum_required(VERSION 3.25)
 project(hello_dpi CXX)
 
+set(CMAKE_CXX_STANDARD 11)
+
 add_library(hello_dpi SHARED
     ./hello.cpp
     )
 
-if(NOT SIMULATOR STREQUAL "verilator")
+if(SIMULATOR STREQUAL "modelsim")
     target_compile_options(hello_dpi PRIVATE -m32)
     target_link_options(hello_dpi PRIVATE -m32)
 endif() 

examples/simple_mixed_language/CMakeLists.txt

@@ -0,0 +1,32 @@
+cmake_minimum_required(VERSION 3.25)
+project(simple_mixed_language NONE)
+
+include("../../SoCMakeConfig.cmake")
+
+option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;vcs;all" "modelsim")
+if(SIMULATOR STREQUAL "all")
+    set(ALL_SIMS TRUE)
+endif()
+
+add_ip(tb
+    DESCRIPTION "Simple verilog testbench")
+
+ip_sources(${IP} VERILOG
+    tb.v)
+
+add_subdirectory(adder)
+ip_link(${IP} adder)
+
+if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
+    modelsim(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS)
+    xcelium(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS)
+    vcs(${IP})
+endif()
+
+help()

examples/modelsim/simple/adder/CMakeLists.txt → examples/simple_mixed_language/adder/CMakeLists.txt

@@ -3,5 +3,5 @@ add_ip(adder
     DESCRIPTION "Just a simple adder")
 
 ip_sources(${IP} VHDL
-    ${CMAKE_CURRENT_LIST_DIR}/adder.vhdl
+    adder.vhdl
     )

examples/modelsim/simple/tb.v → examples/simple_mixed_language/tb.v

@@ -1,15 +1,22 @@
 module tb;
- initial begin
-     $display("Hello world, from SoCMake build system\n");
-     $finish();
- end
-
- wire [4:0] a, b, o;
+ reg [4:0] a, b;
+ wire [4:0] o;
 
  adder adder_i (
      .NUM1(a),
      .NUM2(b),
      .SUM(o)
      );
 
+ initial begin
+     a = 5;
+     b = 10;
+     #1;
+
+     $display("Hello world, from SoCMake build system\n");
+     $display("%d + %d = %d", a, b, o);
+     $finish();
+ end
+
+
  endmodule

examples/simple_verilog/CMakeLists.txt

@@ -0,0 +1,41 @@
+cmake_minimum_required(VERSION 3.25)
+project(simple_verilog_example NONE)
+
+include("../../SoCMakeConfig.cmake")
+
+option_enum(SIMULATOR "Which simulator to use" "iverilog;questa;modelsim;xcelium;vcs;verilator;all" "iverilog")
+if(SIMULATOR STREQUAL "all")
+    set(ALL_SIMS TRUE)
+endif()
+
+add_ip(tb
+    DESCRIPTION "Simple verilog testbench")
+
+ip_sources(${IP} VERILOG
+    tb.v)
+
+add_subdirectory(adder)
+ip_link(${IP} adder)
+
+
+if(SIMULATOR STREQUAL "iverilog" OR ALL_SIMS)
+    iverilog(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim" OR ALL_SIMS)
+    modelsim(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "xcelium" OR ALL_SIMS)
+    xcelium(${IP})
+endif()
+
+if(SIMULATOR STREQUAL "verilator" OR ALL_SIMS)
+    verilator(${IP} MAIN VERILATOR_ARGS --timing)
+endif()
+
+if(SIMULATOR STREQUAL "vcs" OR ALL_SIMS)
+    vcs(${IP})
+endif()
+
+help()

examples/simple_verilog/adder/CMakeLists.txt

@@ -0,0 +1,6 @@
+add_ip(adder
+    DESCRIPTION "Just a simple adder")
+
+ip_sources(${IP} VERILOG
+    adder.v
+    )

examples/simple_verilog/adder/adder.v

@@ -0,0 +1,8 @@
+module adder(
+    input [4:0] NUM1,
+    input [4:0] NUM2,
+    output [4:0] SUM
+    );
+
+    assign SUM = NUM1 + NUM2;
+endmodule

examples/simple_verilog/tb.v

@@ -0,0 +1,22 @@
+module tb;
+ reg [4:0] a, b;
+ wire [4:0] o;
+
+ adder adder_i (
+     .NUM1(a),
+     .NUM2(b),
+     .SUM(o)
+     );
+
+ initial begin
+     a = 5;
+     b = 10;
+     #1;
+
+     $display("Hello world, from SoCMake build system\n");
+     $display("%d + %d = %d", a, b, o);
+     $finish();
+ end
+
+
+ endmodule