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refactor peakrdl_regblock and add tests
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Original file line number | Diff line number | Diff line change |
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@@ -1 +1,2 @@ | ||
add_subdirectory(print) | ||
add_subdirectory(regblock) |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,59 @@ | ||
include("../../../../SoCMakeConfig.cmake") | ||
include("../../../utils/test_utils.cmake") | ||
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cmake_minimum_required(VERSION 3.25) | ||
project(test NONE) | ||
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add_ip(ip) | ||
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ip_sources(${IP} SYSTEMRDL | ||
${CMAKE_CURRENT_LIST_DIR}/ip.rdl | ||
) | ||
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peakrdl_regblock(${IP}) | ||
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include(CTest) | ||
enable_testing() | ||
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find_python3() | ||
add_test_makefile_rule_match_patterns(${IP}_peakrdl_regblock | ||
"${Python3_EXECUTABLE} -m" | ||
"peakrdl regblock" | ||
"--rename ${IP_NAME}_regblock" | ||
"--cpuif apb3-flat" | ||
"-o ${PROJECT_BINARY_DIR}/${IP}_peakrdl_regblock" | ||
"${CMAKE_CURRENT_LIST_DIR}/ip.rdl" | ||
) | ||
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add_ip(ip2) | ||
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ip_sources(${IP} SYSTEMRDL | ||
${CMAKE_CURRENT_LIST_DIR}/ip2.rdl | ||
) | ||
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ip_link(ip2 ip) | ||
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peakrdl_regblock(${IP} | ||
OUTDIR ${PROJECT_BINARY_DIR}/ip2_regblock | ||
INTF axi4-lite | ||
RENAME random_ip | ||
RESET arst_n | ||
ARGS --addr-width 8 | ||
--rt-read-response | ||
) | ||
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include(CTest) | ||
enable_testing() | ||
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find_python3() | ||
add_test_makefile_rule_match_patterns(${IP}_peakrdl_regblock | ||
"${Python3_EXECUTABLE} -m" | ||
"peakrdl regblock" | ||
"--rename random_ip" | ||
"--cpuif axi4-lite" | ||
"--default-reset arst_n" | ||
"--addr-width 8" | ||
"--rt-read-response" | ||
"-o ${PROJECT_BINARY_DIR}/ip2_regblock" | ||
"${CMAKE_CURRENT_LIST_DIR}/ip.rdl ${CMAKE_CURRENT_LIST_DIR}/ip2.rdl" # Keep them in single string to enforce order | ||
) |
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@@ -0,0 +1,18 @@ | ||
addrmap ip { | ||
reg { | ||
regwidth = 32; | ||
field { | ||
hw = rw; sw = rw; | ||
fieldwidth = 32; | ||
} f1; | ||
} r1; | ||
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reg { | ||
regwidth = 32; | ||
field { | ||
hw = r; sw = rw; | ||
fieldwidth = 32; | ||
} f1; | ||
} r2; | ||
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}; |
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addrmap ip2 { | ||
reg { | ||
regwidth = 32; | ||
field { | ||
hw = rw; sw = rw; | ||
fieldwidth = 32; | ||
} f1; | ||
} r1; | ||
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reg { | ||
regwidth = 32; | ||
field { | ||
hw = r; sw = rw; | ||
fieldwidth = 32; | ||
} f1; | ||
} r2; | ||
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}; | ||
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