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Add DPI-C support for XCelium and Verilator (not possible with MAIN a…
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…rgument)
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Risto97 committed Nov 26, 2024
1 parent 25c195b commit a7fe95d
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Showing 9 changed files with 100 additions and 39 deletions.
24 changes: 14 additions & 10 deletions cmake/sim/cadence/xcelium.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
include_guard(GLOBAL)

function(xcelium IP_LIB)
cmake_parse_arguments(ARG "GUI" "" "" ${ARGN})
cmake_parse_arguments(ARG "GUI" "" "ARGS" ${ARGN})
if(ARG_UNPARSED_ARGUMENTS)
message(FATAL_ERROR "${CMAKE_CURRENT_FUNCTION} passed unrecognized argument " "${ARG_UNPARSED_ARGUMENTS}")
endif()
Expand All @@ -28,12 +28,6 @@ function(xcelium IP_LIB)
alias_dereference(IP_LIB ${IP_LIB})
get_target_property(BINARY_DIR ${IP_LIB} BINARY_DIR)

if(ARG_GUI)
set(ARG_GUI -gui)
else()
unset(ARG_GUI)
endif()

get_ip_sources(SOURCES ${IP_LIB} SYSTEMVERILOG VERILOG VHDL)
get_ip_include_directories(INC_DIRS ${IP_LIB} SYSTEMVERILOG VERILOG VHDL)

Expand All @@ -46,6 +40,16 @@ function(xcelium IP_LIB)
list(APPEND CMP_DEFS_ARG -define ${def})
endforeach()

get_ip_links(IPS_LIST ${IP_LIB})

unset(__lib_args)
foreach(ip ${IPS_LIST})
get_target_property(ip_type ${ip} TYPE)
if(ip_type STREQUAL "SHARED_LIBRARY" OR ip_type STREQUAL "STATIC_LIBRARY")
list(APPEND __lib_args -sv_lib $<TARGET_FILE_DIR:${ip}>/lib$<TARGET_FILE_BASE_NAME:${ip}>)
endif()
endforeach()

add_custom_target( run_${IP_LIB}_${CMAKE_CURRENT_FUNCTION}
COMMAND xrun
# Enable parameters without default value
Expand All @@ -54,13 +58,13 @@ function(xcelium IP_LIB)
${SOURCES}
${ARG_INCDIRS}
${CMP_DEFS_ARG}
${ARG_GUI}
${__lib_args}
$<$<BOOL:${ARG_GUI}>:-gui>
${ARG_ARGS}
COMMENT "Running ${CMAKE_CURRENT_FUNCTION} on ${IP_LIB}"
DEPENDS ${SOURCES} ${IP_LIB}
)

# add_dependencies(${IP_LIB}_${CMAKE_CURRENT_FUNCTION} ${IP_LIB})

endfunction()


9 changes: 9 additions & 0 deletions cmake/sim/verilator/verilator.cmake
Original file line number Diff line number Diff line change
Expand Up @@ -194,6 +194,15 @@ function(verilator IP_LIB)

target_link_libraries(${VERILATED_LIB} INTERFACE -pthread)

# Search for linked libraries that are Shared or Static libraries and link them to the verilated library
get_ip_links(IPS_LIST ${IP_LIB})
foreach(ip ${IPS_LIST})
get_target_property(ip_type ${ip} TYPE)
if(ip_type STREQUAL "SHARED_LIBRARY" OR ip_type STREQUAL "STATIC_LIBRARY")
target_link_libraries(${VERILATED_LIB} INTERFACE ${ip})
endif()
endforeach()

string(REPLACE "__" "::" ALIAS_NAME "${VERILATED_LIB}")
add_library(${ALIAS_NAME} ALIAS ${VERILATED_LIB})

Expand Down
33 changes: 33 additions & 0 deletions examples/dpi-c/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
cmake_minimum_required(VERSION 3.25)
project(dpi_example NONE)

include("../../SoCMakeConfig.cmake")

option_enum(SIMULATOR "Which simulator to use" "questa;modelsim;xcelium;verilator" "modelsim")

add_ip(tb
DESCRIPTION "Simple verilog testbench"
)

ip_sources(${IP} SYSTEMVERILOG
${PROJECT_SOURCE_DIR}/tb.sv
)

add_subdirectory(hello)

ip_link(${IP} hello_dpi)

if(SIMULATOR STREQUAL "questa" OR SIMULATOR STREQUAL "modelsim")
modelsim(${IP})

elseif(SIMULATOR STREQUAL "xcelium")
xcelium(${IP})

elseif(SIMULATOR STREQUAL "verilator")
enable_language(CXX)
verilator(${IP})
add_executable(main Vtb__main.cpp)
target_link_libraries(main tb__vlt)
endif()

help()
33 changes: 33 additions & 0 deletions examples/dpi-c/Vtb__main.cpp
Original file line number Diff line number Diff line change
@@ -0,0 +1,33 @@
// Verilated -*- C++ -*-
// DESCRIPTION: main() calling loop, created with Verilator --main

#include "verilated.h"
#include "Vtb.h"

//======================

int main(int argc, char** argv, char**) {
// Setup context, defaults, and parse command line
Verilated::debug(0);
const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
contextp->commandArgs(argc, argv);

// Construct the Verilated model, from Vtop.h generated from Verilating
const std::unique_ptr<Vtb> topp{new Vtb{contextp.get()}};

// Simulate until $finish
while (!contextp->gotFinish()) {
// Evaluate model
topp->eval();
// Advance time
contextp->timeInc(1);
}

if (!contextp->gotFinish()) {
VL_DEBUG_IF(VL_PRINTF("+ Exiting without $finish; no events left\n"););
}

// Final model cleanup
topp->final();
return 0;
}
11 changes: 11 additions & 0 deletions examples/dpi-c/hello/CMakeLists.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
cmake_minimum_required(VERSION 3.25)
project(hello_dpi CXX)

add_library(hello_dpi SHARED
./hello.cpp
)

if(NOT SIMULATOR STREQUAL "verilator")
target_compile_options(hello_dpi PRIVATE -m32)
target_link_options(hello_dpi PRIVATE -m32)
endif()
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20 changes: 0 additions & 20 deletions examples/modelsim/dpi/CMakeLists.txt

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9 changes: 0 additions & 9 deletions examples/modelsim/dpi/hello/CMakeLists.txt

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