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!IMPORTANT!: It is strongly recommended to save previous library version for debugging early implemented designs. It is NOT ALLOWED simple cell layout replacement in existing designs. Designs require re-synthesis of layout.
M2 was removed from following cells:
sg13g2_buf_16 area: no changes
sg13g2_dfrbp_1 area: new value is 52.6176 um2
sg13g2_dfrbp_2 area: no changes
sg13g2_ebufn_4 area: new value is 27.216 um2
sg13g2_inv_16 area: no changes
sg13g2_slgcp_1 area: no changes
Cell sg13g2_sdfbbp_1 is not changed full re-design required
(will be re-designed). sg13g2_dfrbp_1 cell requires area optimization. It will be done together with scan flip-flop re-design.
Layout cleanup was provided for all cells (contacts alignment and pin placement optimization). Issues NW.b violation when two ebufn_2 abutt themselves #246 , Better alignment and clearer structures of std_cell #311 , decap cells should be marked "CORE SPACER" in lef #237 , Fix pin labels in
a221oi_1
cell #167 ,M1.b
violation whendllr_1
is abutted with other cells #268 (can be overlaped with previously solved issues)multiplier m=1 for all transistors, NG parameter is used now in CDL. Issue Stdcell schematics must contain multiplier = 1 #180
List of updated views: CDL, GDS, LEF, Liberty (cells area updated, re-CZ is NOT! provided yet).