Resolve github issues. #69
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Add `$(BOARD_SERIAL_PORT)` makefile variable to configure which serial port for the `console.py` to use. Each board sets this variable in the corresponding `board.mk` file. The user may set a serial port for each board by adding environment variables for each one in the runner machine. For example: ``` export CYC5_SERIAL_PORT=/dev/ttyUSB0 export Z7_SERIAL_PORT=/dev/ttyUSB2 ``` Resolves issue #60
WIP: Comment async FIFOs code while not ready.
Related to issue: #61
Rename bsp.vh and fpga wrappers as requested. New board.py files work as a new module and should be called by the core using its `blocks` list with `instantiate: False` TODO: Update Makefile scripts to use files generated by corresponding board.py
Merge `interface` wire/port attribute into `signals`. Resolves issue #65 - If list is passed to signals then it will be interpreted as a list of signals. - If dictionary is passed to signals then it will be interpreted as an if_gen.py interface.
Resolves issue IObundle/iob-soc#947
Resolves issue #67 New version of iob_system always contains an internal memory (axi_ram) in the iob_system memory wrapper. If USE_EXTMEM=1, iob_system will also have an extra "axi" interface for the DDR memory. If USE_EXTMEM=1 during simulation, the axi interface will be unconnected in the simulation wrapper. If USE_EXTMEM=0, iob_system has the following address ranges: [0x00000000-0x3FFFFFFF]: Internal Memory (30 bits) [0x40000000-0x7FFFFFFF]: Bootrom (30 bits) [0x80000000-0xFFFFFFFF]: Peripherals (uncached) (31 bits) If USE_EXTMEM=1, iob_system has the following address ranges: [0x00000000-0x1FFFFFFF]: Internal Memory (29 bits) [0x20000000-0x3FFFFFFF]: External Memory (29 bits) <- DDR axi interface [0x40000000-0x7FFFFFFF]: Bootrom (30 bits) [0x80000000-0xFFFFFFFF]: Peripherals (uncached) (31 bits)
Related to issue #67 - Ignore INIT_MEM value for USE_EXTMEM=1 in FPGAs. - Force xilinx interconnect to always have 1 slave (no longer configurable).
Revert ignore script from commit eaeb9ac New iob_system version always has an internal memory that can be initialized. So we can still use INIT_MEM=1 to initialize it, even if we have another external memory on the FPGAs.
By having an individual name for each board wrapper, we can setup multiple boards in one project using py2. If all modules had the same name (like 'board.py'), then calling the setup for the 'board' module would only setup one of them. Update bootloader DDR message to reflect new iob_system with internal memory.
New name is more consistent with FPGA boards. Each fpga board follows `<board_name>.py`. And since every simulation users the same wrapper, then `simulation.py` seems like a good name. Similar case for the `synthesis.py` wrapper.
…N_WRITE; Set internal memory size based on iob_system's 'fw_addr_w' python parameter. Fix axi_ram 'READ_ON_WRITE' verilog parameter based on 'IOB_MEM_NO_READ_ON_WRITE' macro from bsp.vh.
…_conf to "NA" Fix build dir Makefile to generate `bsp.vh` from corresponding board/simulation wrapper `*_conf.vh` Resolves issue #61
Resolves issue IObundle/iob-soc#611 Updated aes_ku040_db_g.py script to generate constraints according to iob_system python parameters. This fixes the following critical warning: `CRITICAL WARNING: [Constraints 18-1056] Clock 'clk' completely overrides clock 'c0_sys_clk_clk_p_i'` Ethernet constraints are currently commented, but can be resolved using the same solution.
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these 136-file PR are impossible to review |
Add `.ignore_file_headers` file for header manager script
Rename fpga and simulation wrappers to use unique names with the core's name as a prefix. For example, the iob_system ku040 wrapper is named `iob_system_aes_ku040_db_g`. Add simulation wrappers to blocks list of lib modules. Most modules use the default py2hwsw `iob_sim` wrapper. This is a generic wrapper that contains the old `bsp.vh` macros.
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$(BOARD_SERIAL_PORT)makefile variable to configure which serial port for theconsole.pyto use.Resolves issue SERIAL_PORT #60.
iob_csrs_democore.Along with previous commits, this should resolve issues CSRS / insert fifos automatically #34, csrs/support register files automatically #33, and Add support for the use of regfiles in swregs iob-soc#719.
interfacewire/port attribute intosignals.Resolves issue change "interface" to "signals" #65.
Resolves issue clang format iob-soc#947
Resolves issue use 2-tuple in connections, not n-tuple #66.
Resolves issue iob_system structure is wrong #67.
bsp.vhmacros to.py. Generatebsp.vhin build dir from corresponding board/simulation wrapper*_conf.vh.Resolves issue change BSP origin #61.
Resolves issue Vivado.log critical errors related to the Ethernet and the "clk" constrains iob-soc#611.