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Libero SoC 2023.2 designs - v1.0

Libero Scripted Designs Update for v2023.2
MIV_RV32 in the designs has been updated from: v3.1.100 to v3.1.200.
MIV_ESS in the designs has been updated from: v2.0.100 to v2.0.200.
Updated Out-of-box example using the CoreTimer example for MIV_RV32. After programming the bitstream, software boots out of the box from the LSRAM.
FlashPro_Express_Projects have been updated to reflect the latest design changes
Readme files updated.

---------

Co-authored-by: Sebastian Slowikowski - M52413 <[email protected]>
Co-authored-by: Ciaran Lappin <[email protected]>
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@CLappin @seb-slowik
3 people authored Nov 2, 2023
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6 changes: 3 additions & 3 deletions FlashPro_Express_Projects/README.md
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# PolarFire Evaluation Kit FPGA Programming Files

This folder contains FlashPro Express v2023.1 projects for the PolarFire Evaluation Kit Mi-V sample designs.
This folder contains FlashPro Express v2023.2 projects for the PolarFire Evaluation Kit Mi-V sample designs.

## Notice
1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples.
1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples.

2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.

.macro STORE_CONTEXT
addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
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2 changes: 1 addition & 1 deletion Libero_Projects/PF_Eval_Kit_MIV_RV32_BaseDesign.tcl
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Expand Up @@ -19,7 +19,7 @@ set validConfigs [list "CFG1" "CFG2" "CFG3" "CFG4" "DGC1" "DGC3" "DGC4"]
set validDesignFlows [list "SYNTHESIZE" "PLACE_AND_ROUTE" "GENERATE_BITSTREAM" "EXPORT_PROGRAMMING_FILE"]
set validDieTypes [list "PS" "ES" ""]
set sdName {BaseDesign}
set exProgramHex "miv-rv32i-systick-blinky.hex"
set exProgramHex "miv-rv32-coretimer-timer_interrupt.hex"

# Call procedures to validate user arguments
set config [verify_config $config]
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6 changes: 3 additions & 3 deletions Libero_Projects/README.md
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# PolarFire Evaluation Kit Mi-V Sample FPGA Designs
This folder contains Tcl scripts that build Libero SoC v2023.1 design projects for the PolarFire Evaluation Kit. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.
This folder contains Tcl scripts that build Libero SoC v2023.2 design projects for the PolarFire Evaluation Kit. These scripts are executed in Libero SoC to generate the sample designs. All Configuration (CFG) design cores boot from memory at 0x8000_0000.

> MI-V Extended Subsystem Design Guide Configurations:
> * For **Design Guide Configuration - DGC1: SPI Write & Boot** refer to this [DGC1 README](../docs//design_dgc1/README.md)
> * For **Design Guide Configuration - DGC3: PF uPROM Boot** refer to this [DGC3 README](../docs//design_dgc3/README.md)
> * For **Design Guide Configuration - DGC4: Basic Peripherals** refer to this [DGC4 README](../docs//design_dgc4/README.md)
## Notice
1) Due to an issues found in the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may continue to use MIV_RV32 v3.0 with FreeRTOS examples.
1) Due to an issue specific to the MIV_RV32 v3.1.100 with the MTVECs address, it is not recommended to use MIV_RV32 v3.1.100 for any FreeRTOS examples. You may use MIV_RV32 v3.0 or the latest MIV_RV32 v3.1.200 with the FreeRTOS examples.

2) There is also an issue which effects all MIV_RV32 cores, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below untill the issue is fixed in the IP.
2) There is also an issue which effects all MIV_RV32 cores up to v3.1.100, when using fast interrupts where the return address can become corrupted. There software workaround can be applied in the entry.S in MIV_RV32 HAL file as shown below until the issue is fixed in the IP.

.macro STORE_CONTEXT
addi sp, sp, -SP_SHIFT_OFFSET*REGBYTES
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/CoreAHBL_C0.tcl
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# Exporting core CoreAHBL_0 to TCL
# Exporting Create design command for core CoreAHBL_0
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {CoreAHBL_C0} -params {\
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {CoreAHBL_C0} -params {\
"HADDR_SHG_CFG:1" \
"M0_AHBSLOT0ENABLE:false" \
"M0_AHBSLOT1ENABLE:false" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/MIV_ESS_C0.tcl
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# Family: PolarFire
# Part Number: MPF300TS-FCG484I
# Create and Configure the core component MIV_ESS_0
create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -download_core -component_name {MIV_ESS_C0} -download_core -params {\
create_and_configure_core -core_vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -download_core -component_name {MIV_ESS_C0} -download_core -params {\
"APBSLOT11ENABLE:false" \
"APBSLOT12ENABLE:false" \
"APBSLOT13ENABLE:false" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/MIV_RV32_CFG1_C0.tcl
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# Exporting core MIV_RV32_CFG1_0 to TCL
# Exporting Create design command for core MIV_RV32_CFG1_0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG1_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:1" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/MIV_RV32_CFG2_C0.tcl
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# Exporting core MIV_RV32_CFG2_0 to TCL
# Exporting Create design command for core MIV_RV32_CFG2_0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG2_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:0" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/MIV_RV32_CFG3_C0.tcl
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# Exporting core MIV_RV32_CFG3_0 to TCL
# Exporting Create design command for core MIV_RV32_CFG3_0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_CFG3_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:0" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/cfg4/AHBL_bus.tcl
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# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component AHBL_bus
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -download_core -component_name {AHBL_bus} -params {\
create_and_configure_core -core_vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -download_core -component_name {AHBL_bus} -params {\
"HADDR_SHG_CFG:1" \
"M0_AHBSLOT0ENABLE:true" \
"M0_AHBSLOT1ENABLE:true" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/cfg4/MIV_RV32_C0.tcl
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# Family: PolarFire
# Part Number: MPF300TS-1FCG1152I
# Create and Configure the core component MIV_RV32_C0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x6fff" \
"AHB_INITIATOR_TYPE:1" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/dgc/MIV_RV32_DGC1_C0.tcl
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# Create and Configure the core component MIV_RV32_DGC1_C0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_DGC1_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_DGC1_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:1" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/dgc/MIV_RV32_DGC3_C0.tcl
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# Create and Configure the core component MIV_RV32_DGC3_C0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_DGC3_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_DGC3_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:1" \
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2 changes: 1 addition & 1 deletion Libero_Projects/import/components/dgc/MIV_RV32_DGC4_C0.tcl
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Expand Up @@ -2,7 +2,7 @@
# Family: PolarFire
# Part Number: MPF300T-FCG1152I
# Create and Configure the core component MIV_RV32_DGC4_C0
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -download_core -component_name {MIV_RV32_DGC4_C0} -params {\
create_and_configure_core -core_vlnv {Microsemi:MiV:MIV_RV32:3.1.200} -download_core -component_name {MIV_RV32_DGC4_C0} -params {\
"AHB_END_ADDR_0:0xffff" \
"AHB_END_ADDR_1:0x8fff" \
"AHB_INITIATOR_TYPE:1" \
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9 changes: 4 additions & 5 deletions Libero_Projects/import/proc_blocks.tcl
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Expand Up @@ -190,11 +190,10 @@ proc download_required_direct_cores {hwPlatform softCpu config} {
download_core -vlnv {Actel:DirectCore:COREAXITOAHBL:3.6.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAPB3:4.2.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:COREAHBTOAPB3:3.2.101} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAHBLite:5.6.105} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:DirectCore:CoreAHBLite:6.1.101} -location {www.microchip-ip.com/repositories/DirectCore}
if {$softCpu eq "MIV_RV32"} {
download_core -vlnv {Microsemi:MiV:MIV_RV32:3.1.100} -location {www.microchip-ip.com/repositories/DirectCore}
download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.100} -location {www.microchip-ip.com/repositories/SgCore}
download_core -vlnv {Microsemi:MiV:MIV_RV32:3.2.100} -location {www.microchip-ip.com/repositories/DirectCore}

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@minhtue1996

minhtue1996 Nov 14, 2023

@seb-slowik @CLappin Hi, I think there is a typo here. The version for MIV_RV32 should be 3.1.200 according to the other files, but here it's 3.2.100.

On a separate but related note, this function "download_required_direct_cores" is actually never used (for example, it's explicitly commented out in https://github.com/Mi-V-Soft-RISC-V/PolarFire-Eval-Kit/blob/main/Libero_Projects/PF_Eval_Kit_MIV_RV32_BaseDesign.tcl#L77), so everything would work, but I think we should still make it correct.

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@CLappin

CLappin Nov 14, 2023

Author Contributor

Hi @minhtue1996
Thank you for catching this, we will update and try get a release out for this as soon as possible.

Thanks,
Ciaran
download_core -vlnv {Actel:SystemBuilder:MIV_ESS:2.0.200} -location {www.microchip-ip.com/repositories/SgCore}
}
if {$softCpu eq "MIV_RV32IMA_L1_AHB"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AHB:2.3.100} -location {www.microchip-ip.com/repositories/DirectCore} }
if {$softCpu eq "MIV_RV32IMA_L1_AXI"} {download_core -vlnv {Microsemi:MiV:MIV_RV32IMA_L1_AXI:2.1.100} -location {www.microchip-ip.com/repositories/DirectCore} }
Expand Down Expand Up @@ -241,4 +240,4 @@ proc run_verify_timing { } {
run_tool -name {VERIFYTIMING}
}
# Procedure blocks end
#
#
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