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fix:update fpga dfl ioctl changes and bug fixes #3021

Merged
merged 6 commits into from
Oct 12, 2023
Merged

fix:update fpga dfl ioctl changes and bug fixes #3021

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6137a8e
fix:update fpga dfl ioctl changes and bug fixes
anandaravuri Oct 5, 2023
e5afef2
Merge branch 'master' into aravuri/cxl_he_cache_bugfix_1
anandaravuri Oct 10, 2023
ef4391c
fix: add command line input bias and support multiple he-cache instances
anandaravuri Oct 10, 2023
67236d6
Merge branch 'master' into aravuri/cxl_he_cache_bugfix_1
anandaravuri Oct 12, 2023
71673eb
fix: set stride to 3 for fpga rd/wr cache hit/miss
anandaravuri Oct 12, 2023
7053b71
Merge branch 'master' into aravuri/cxl_he_cache_bugfix_1
anandaravuri Oct 12, 2023
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2 changes: 0 additions & 2 deletions libraries/plugins/xfpga/fpga-dfl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -371,7 +371,6 @@ struct dfl_cxl_cache_region_info {
* @flags: flags
* @user_addr: user mmap virtual address
* @length: length of mapping (bytes)
* @numa_node: Numa node number
* @csr_array: array of region address offset
*
* maps user allocated virtual address to physical address.
Expand All @@ -381,7 +380,6 @@ struct dfl_cxl_cache_buffer_map {
__u32 flags;
__u64 user_addr;
__u64 length;
__u32 numa_node;
__u64 csr_array[DFL_ARRAY_MAX_SIZE];
};

Expand Down
89 changes: 35 additions & 54 deletions samples/cxl_host_exerciser/cxl_he_cache_cmd.h
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Original file line number Diff line number Diff line change
Expand Up @@ -123,9 +123,9 @@ class he_cache_cmd : public he_cmd {
// HE_INFO
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_32KB_CACHE_LINES);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

cout << "Read number Lines:" << FPGA_32KB_CACHE_LINES << endl;
cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
cout << "Numa node:" << numa_node_ << endl;
Expand Down Expand Up @@ -156,10 +156,7 @@ class he_cache_cmd : public he_cmd {
}

// Start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand All @@ -170,7 +167,7 @@ class he_cache_cmd : public he_cmd {
return -1;
}

he_perf_counters();
he_perf_counters(HE_CXL_RD_LATENCY);

cout << "********** AFU Copied host cache to FPGA Cache successfully "
"********** " << endl;
Expand All @@ -188,10 +185,7 @@ class he_cache_cmd : public he_cmd {
host_exe_->write64(HE_RD_ADDR_TABLE_CTRL, rd_table_ctl_.value);

// Start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand All @@ -202,7 +196,7 @@ class he_cache_cmd : public he_cmd {
return -1;
}

he_perf_counters();
he_perf_counters(HE_CXL_RD_LATENCY);
host_exe_->free_dsm();
host_exe_->free_cache_read();

Expand Down Expand Up @@ -230,9 +224,9 @@ class he_cache_cmd : public he_cmd {
// HE_INFO
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_32KB_CACHE_LINES);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

cout << "Read/write number Lines:" << FPGA_32KB_CACHE_LINES << endl;
cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
cout << "Write address table size:" << he_info_.write_addr_table_size
Expand Down Expand Up @@ -264,10 +258,7 @@ class he_cache_cmd : public he_cmd {
}

// Start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand All @@ -294,13 +285,10 @@ class he_cache_cmd : public he_cmd {
wr_table_ctl_.value = 0;
wr_table_ctl_.enable_address_stride = 1;
host_exe_->write64(HE_WR_ADDR_TABLE_CTRL, wr_table_ctl_.value);
host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES);

host_exe_->write64(HE_WR_NUM_LINES, FPGA_32KB_CACHE_LINES);
// Start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand Down Expand Up @@ -337,9 +325,9 @@ class he_cache_cmd : public he_cmd {
// HE_INFO
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_2MB_CACHE_LINES);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

cout << "Read number Lines:" << FPGA_2MB_CACHE_LINES << endl;
cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;

Expand Down Expand Up @@ -368,11 +356,8 @@ class he_cache_cmd : public he_cmd {
return -1;
}

// start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand All @@ -383,7 +368,7 @@ class he_cache_cmd : public he_cmd {
return -1;
}

he_perf_counters();
he_perf_counters(HE_CXL_RD_LATENCY);
host_exe_->free_cache_read();
host_exe_->free_dsm();

Expand All @@ -407,9 +392,9 @@ class he_cache_cmd : public he_cmd {
// HE_INFO
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_WR_NUM_LINES, FPGA_2MB_CACHE_LINES);
host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES);

cout << "Read/write number Lines:" << FPGA_2MB_CACHE_LINES << endl;
cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
cout << "Write address table size:" << he_info_.write_addr_table_size
Expand Down Expand Up @@ -440,11 +425,8 @@ class he_cache_cmd : public he_cmd {
return -1;
}

// start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand All @@ -467,7 +449,7 @@ class he_cache_cmd : public he_cmd {

int he_run_host_rd_cache_hit_test() {

cout << "********** 1 Host LLC Read cache hit test start**********" << endl;
cout << "********** Host LLC Read cache hit test start**********" << endl;
/*
STEPS
1) Allocate DSM, Read buffer
Expand All @@ -479,9 +461,9 @@ class he_cache_cmd : public he_cmd {
// HE_INFO
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_32KB_CACHE_LINES);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES);

cout << "Read number Lines:" << FPGA_32KB_CACHE_LINES << endl;
cout << "Read number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
cout << "Write address table size:" << he_info_.write_addr_table_size
Expand Down Expand Up @@ -513,14 +495,11 @@ class he_cache_cmd : public he_cmd {
}

cout << " create thread - moves read buffer to host cache " << endl;
std::thread t1(he_cache_thread, host_exe_->get_read(), BUFFER_SIZE_2MB);
std::thread t1(he_cache_thread, host_exe_->get_read(), BUFFER_SIZE_32KB);
sleep(1);

// start
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
// Start test
he_start_test();

// wait for completion
if (!he_wait_test_completion()) {
Expand All @@ -537,7 +516,7 @@ class he_cache_cmd : public he_cmd {
g_stop_thread = true;
t1.join();

he_perf_counters();
he_perf_counters(HE_CXL_RD_LATENCY);
sleep(1);
host_exe_->free_cache_read();
host_exe_->free_dsm();
Expand All @@ -564,8 +543,8 @@ class he_cache_cmd : public he_cmd {
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);

host_exe_->write64(HE_WR_NUM_LINES, FPGA_32KB_CACHE_LINES);
cout << "Write number Lines:" << FPGA_32KB_CACHE_LINES << endl;
host_exe_->write64(HE_WR_NUM_LINES, FPGA_512CACHE_LINES);
cout << "Write number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
cout << "Write address table size:" << he_info_.write_addr_table_size
Expand Down Expand Up @@ -597,7 +576,7 @@ class he_cache_cmd : public he_cmd {
}

cout << " create thread - moves read buffer to host cache " << endl;
std::thread t1(he_cache_thread, host_exe_->get_write(), BUFFER_SIZE_2MB);
std::thread t1(he_cache_thread, host_exe_->get_write(), BUFFER_SIZE_32KB);
sleep(1);

// start
Expand Down Expand Up @@ -645,8 +624,8 @@ class he_cache_cmd : public he_cmd {
// HE_INFO
// Set Read number Lines
he_info_.value = host_exe_->read64(HE_INFO);
host_exe_->write64(HE_RD_NUM_LINES, FPGA_32KB_CACHE_LINES - 1);
cout << "Read/write number Lines:" << FPGA_32KB_CACHE_LINES - 1 << endl;
host_exe_->write64(HE_RD_NUM_LINES, FPGA_512CACHE_LINES );
cout << "Read/write number Lines:" << FPGA_512CACHE_LINES << endl;
cout << "Line Repeat Count:" << he_linerep_count_ << endl;
cout << "Read address table size:" << he_info_.read_addr_table_size << endl;
cout << "Write address table size:" << he_info_.write_addr_table_size
Expand Down Expand Up @@ -692,7 +671,7 @@ class he_cache_cmd : public he_cmd {
return -1;
}

he_perf_counters();
he_perf_counters(HE_CXL_RD_LATENCY);
host_exe_->free_cache_read();
host_exe_->free_dsm();

Expand Down Expand Up @@ -796,6 +775,8 @@ class he_cache_cmd : public he_cmd {
he_ctl_.ResetL = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);

print_csr();

if (he_test_all_ == true) {
int retvalue = 0;
ret = he_run_fpga_rd_cache_hit_test();
Expand Down
97 changes: 96 additions & 1 deletion samples/cxl_host_exerciser/cxl_he_cmd.h
View file
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Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ class he_cmd : public test_command {
return (double)(num_lines * 64) / ((1000.0 / he_clock_mhz_ * num_ticks));
}

void he_perf_counters() {
void he_perf_counters(he_cxl_latency cxl_latency = HE_CXL_LATENCY_NONE) {
volatile he_cache_dsm_status *dsm_status = NULL;

dsm_status = reinterpret_cast<he_cache_dsm_status *>(
Expand Down Expand Up @@ -81,9 +81,95 @@ class he_cmd : public test_command {
host_exe_->logger_->info("Bandwidth: {0:0.3f} GB/s", perf_data);
}

if (cxl_latency == HE_CXL_RD_LATENCY) {
if (dsm_status->num_ticks > 0 && dsm_status->num_reads > 0) {
double latency = (double)((dsm_status->num_ticks / (double)dsm_status->num_reads)
*( 2.5));

host_exe_->logger_->info("Read Latency : {0:0.2f} nanoseconds", latency);
}
else {
host_exe_->logger_->info("Read Latency: N/A");
}
}

cout << "********* DSM Status CSR end *********" << endl;
}

void print_csr() {

host_exe_->logger_->debug("HE_DFH:0x{:x}", host_exe_->read64(HE_DFH));
host_exe_->logger_->debug("HE_ID_L:0x{:x}", host_exe_->read64(HE_ID_L));
host_exe_->logger_->debug("HE_ID_H:0x{:x}", host_exe_->read64(HE_ID_H));

host_exe_->logger_->debug("HE_SCRATCHPAD0:0x{:x}",
host_exe_->read64(HE_SCRATCHPAD0));

host_exe_->logger_->debug("HE_DSM_BASE:0x{:x}", host_exe_->read64(HE_DSM_BASE));

host_exe_->logger_->debug("HE_CTL:0x{:x}", host_exe_->read64(HE_CTL));

host_exe_->logger_->debug("HE_INFO:0x{:x}", host_exe_->read64(HE_INFO));

host_exe_->logger_->debug("HE_WR_NUM_LINES:0x{:x}",
host_exe_->read64(HE_WR_NUM_LINES));

host_exe_->logger_->debug("HE_WR_BYTE_ENABLE:0x{:x}",
host_exe_->read64(HE_WR_BYTE_ENABLE));

host_exe_->logger_->debug("HE_WR_CONFIG:0x{:x}",
host_exe_->read64(HE_WR_CONFIG));

host_exe_->logger_->debug("HE_WR_ADDR_TABLE_CTRL:0x{:x}",
host_exe_->read64(HE_WR_ADDR_TABLE_CTRL));

host_exe_->logger_->debug("HE_WR_ADDR_TABLE_DATA:0x{:x}",
host_exe_->read64(HE_WR_ADDR_TABLE_DATA));

host_exe_->logger_->debug("HE_RD_NUM_LINES:0x{:x}",
host_exe_->read64(HE_RD_NUM_LINES));

host_exe_->logger_->debug("HE_RD_CONFIG:0x{:x}",
host_exe_->read64(HE_WR_CONFIG));
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host_exe_->logger_->debug("HE_RD_ADDR_TABLE_CTRL:0x{:x}",
host_exe_->read64(HE_RD_ADDR_TABLE_CTRL));

host_exe_->logger_->debug("HE_RD_ADDR_TABLE_DATA:0x{:x}",
host_exe_->read64(HE_RD_ADDR_TABLE_DATA));

host_exe_->logger_->debug("HE_ERROR_STATUS:0x{:x}",
host_exe_->read64(HE_ERROR_STATUS));

host_exe_->logger_->debug("HE_ERROR_EXP_DATA:0x{:x}",
host_exe_->read64(HE_ERROR_EXP_DATA));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA0:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA0));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA1:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA1));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA2:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA2));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA3:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA3));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA4:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA4));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA5:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA5));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA6:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA6));

host_exe_->logger_->debug("HE_ERROR_ACT_DATA7:0x{:x}",
host_exe_->read64(HE_ERROR_ACT_DATA7));

}

void host_exerciser_errors() {
he_err_status err_status;
uint64_t err = 0;
Expand Down Expand Up @@ -152,6 +238,15 @@ class he_cmd : public test_command {
return true;
}

void he_start_test() {
// start test
he_ctl_.Start = 1;
host_exe_->write64(HE_CTL, he_ctl_.value);
he_ctl_.Start = 0;
host_exe_->write64(HE_CTL, he_ctl_.value);
Comment on lines +261 to +262
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This seems odd. I think that the hardware would want to clear the bit once the test was started. That way, software could check whether the hardware has started. May want to raise this to the hw team.

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fixed


}

bool verify_numa_node() {

if (numa_available() < 0) {
Expand Down
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