fix(mem): generate if for RAMS when HEXFILE="none"

- addresses IObundle#95
P-Miranda · Dec 27, 2024 · cd002cb · cd002cb
1 parent 617b18d
commit cd002cb
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Showing 13 changed files with 85 additions and 34 deletions.
diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_at2p/iob_ram_at2p.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_at2p/iob_ram_at2p.py
@@ -109,17 +109,18 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (HEXFILE != "none") ? 1 : 0;
             // Declare the RAM
    reg [DATA_W-1:0] ram[(2**ADDR_W)-1:0];
    reg [DATA_W-1:0] r_data_o_reg;
    assign r_data_o=r_data_o_reg;
 
    // Initialize the RAM
-   initial begin
-       if (MEM_INIT_FILE_INT != "none") begin
-           $readmemh(MEM_INIT_FILE_INT, ram, 0, (2 ** ADDR_W) - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, ram, 0, (2 ** ADDR_W) - 1);
        end
-   end
+   endgenerate
 
    //write
    always @(posedge w_clk_i) begin

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_atdp/iob_ram_atdp.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_atdp/iob_ram_atdp.py
@@ -137,6 +137,7 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
             // Declare the RAM
    reg [DATA_W-1:0] ram[2**ADDR_W-1:0];
    reg [DATA_W-1:0] dA_o_reg;
@@ -145,7 +146,11 @@ def setup(py_params_dict):
     assign dB_o=dB_o_reg;
 
    // Initialize the RAM
-   initial if (MEM_INIT_FILE_INT != "none") $readmemh(MEM_INIT_FILE_INT, ram, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, ram, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    //read port
    always @(posedge clkA_i) begin  // Port A

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_atdp_be/iob_ram_atdp_be.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_atdp_be/iob_ram_atdp_be.py
@@ -183,15 +183,20 @@ def setup(py_params_dict):
    endgenerate
 `else  // !IOB_MEM_NO_READ_ON_WRITE
    // this allow ISE 14.7 to work; do not remove
+   localparam INIT_RAM = (mem_init_file_int != "none.hex") ? 1 : 0;
    localparam mem_init_file_int = {HEXFILE, ".hex"};
 
    // Core Memory
    reg [DATA_W-1:0] ram_block[(2**ADDR_W)-1:0];
 
    // Initialize the RAM
-   initial
-      if (mem_init_file_int != "none.hex")
-         $readmemh(mem_init_file_int, ram_block, 0, 2 ** ADDR_W - 1);
+   generate
+        if (INIT_RAM) begin : mem_init
+           initial
+              if (mem_init_file_int != "none.hex")
+                 $readmemh(mem_init_file_int, ram_block, 0, 2 ** ADDR_W - 1);
+        end
+   endgenerate
 
    // Port-A Operation
    reg     [DATA_W-1:0] dA_o_int;

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_sp/iob_ram_sp.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_sp/iob_ram_sp.py
@@ -95,13 +95,18 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
             // Declare the RAM
    reg [DATA_W-1:0] ram[2**ADDR_W-1:0];
    reg [DATA_W-1:0] d_o_reg;
    assign d_o=d_o_reg;
 
    // Initialize the RAM
-   initial if (MEM_INIT_FILE_INT != "none") $readmemh(MEM_INIT_FILE_INT, ram, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, ram, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    // Operate the RAM
    always @(posedge clk_i)

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_sp_be/iob_ram_sp_be.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_sp_be/iob_ram_sp_be.py
@@ -85,7 +85,7 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
-            
+
    // Operation
 `ifdef IOB_MEM_NO_READ_ON_WRITE
    localparam file_suffix = {"7", "6", "5", "4", "3", "2", "1", "0"};
@@ -113,15 +113,19 @@ def setup(py_params_dict):
    endgenerate
 `else  // !IOB_MEM_NO_READ_ON_WRITE
    // this allows ISE 14.7 to work; do not remove
+   localparam INIT_RAM = (HEXFILE != "none") ? 1 : 0;
    localparam mem_init_file_int = {HEXFILE, ".hex"};
 
    // Core Memory
    reg [DATA_W-1:0] ram_block[(2**ADDR_W)-1:0];
 
    // Initialize the RAM
-   initial
-      if (mem_init_file_int != "none.hex")
-         $readmemh(mem_init_file_int, ram_block, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial
+              $readmemh(mem_init_file_int, ram_block, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    reg     [DATA_W-1:0] d_o_int;
    integer              i;

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_sp_se/iob_ram_sp_se.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_sp_se/iob_ram_sp_se.py
@@ -85,7 +85,7 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
-            
+
 
    // Operation
 `ifdef IOB_MEM_NO_READ_ON_WRITE
@@ -114,15 +114,20 @@ def setup(py_params_dict):
    endgenerate
 `else  // !IOB_MEM_NO_READ_ON_WRITE
    // this allows ISE 14.7 to work; do not remove
+   localparam INIT_RAM = (HEXFILE != "none") ? 1 : 0;
    localparam mem_init_file_int = {HEXFILE, ".hex"};
 
    // Core Memory
    reg [DATA_W-1:0] ram_block[(2**ADDR_W)-1:0];
 
    // Initialize the RAM
-   initial
-      if (mem_init_file_int != "none.hex")
-         $readmemh(mem_init_file_int, ram_block, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial
+              if (mem_init_file_int != "none.hex")
+                 $readmemh(mem_init_file_int, ram_block, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    reg     [DATA_W-1:0] d_o_int;
    integer              i;

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_t2p/iob_ram_t2p.py
@@ -102,19 +102,20 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
-            
 
 
+
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
    // Declare the RAM
    reg [DATA_W-1:0] mem    [(2**ADDR_W)-1:0];
 
    reg [DATA_W-1:0] r_data;
    // Initialize the RAM
-   initial begin
-       if (MEM_INIT_FILE_INT != "none") begin
-           $readmemh(MEM_INIT_FILE_INT, mem, 0, (2 ** ADDR_W) - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, mem, 0, (2 ** ADDR_W) - 1);
        end
-   end
+   endgenerate
 
    //read port
    always @(posedge clk_i) begin

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_t2p_be/iob_ram_t2p_be.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_t2p_be/iob_ram_t2p_be.py
@@ -145,13 +145,19 @@ def setup(py_params_dict):
    endgenerate
 `else  // !IOB_MEM_NO_READ_ON_WRITE
    //this allows ISE 14.7 to work; do not remove
+   localparam INIT_RAM = (HEXFILE != "none") ? 1 : 0;
    localparam mem_init_file_int = HEXFILE;
 
    // Declare the RAM
    reg [DATA_W-1:0] mem[(2**ADDR_W)-1:0];
 
    // Initialize the RAM
-   initial if (mem_init_file_int != "none") $readmemh(mem_init_file_int, mem, 0, (2 ** ADDR_W) - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial
+                $readmemh(mem_init_file_int, mem, 0, (2 ** ADDR_W) - 1);
+       end
+   endgenerate
 
    //read port
    always @(posedge clk_i) if (r_en_i) r_data_o_reg <= mem[r_addr_i];

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_tdp/iob_ram_tdp.py
@@ -138,6 +138,7 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+    localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
     reg [DATA_W-1:0] dA_o_reg;
     reg [DATA_W-1:0] dB_o_reg;
     assign dA_o=dA_o_reg;
@@ -146,7 +147,11 @@ def setup(py_params_dict):
    reg [DATA_W-1:0] ram[2**ADDR_W-1:0];
 
    // Initialize the RAM
-   initial if (MEM_INIT_FILE_INT != "none") $readmemh(MEM_INIT_FILE_INT, ram, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, ram, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    generate
       if (MEM_NO_READ_ON_WRITE) begin : with_MEM_NO_READ_ON_WRITE

diff --git a/py2hwsw/lib/hardware/memories/ram/iob_ram_tdp_be_xil/iob_ram_tdp_be_xil.py b/py2hwsw/lib/hardware/memories/ram/iob_ram_tdp_be_xil/iob_ram_tdp_be_xil.py
@@ -98,13 +98,16 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none.hex") ? 1 : 0;
              // Core Memory
    reg [DATA_W-1:0] ram_block[(2**ADDR_W)-1:0];
 
    // Initialize the RAM
-   initial
-      if (MEM_INIT_FILE_INT != "none.hex")
-         $readmemh(MEM_INIT_FILE_INT, ram_block, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, ram_block, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    // Port-A Operation
    reg     [DATA_W-1:0] dA_o_int;

diff --git a/py2hwsw/lib/hardware/memories/rom/iob_rom_atdp/iob_rom_atdp.py b/py2hwsw/lib/hardware/memories/rom/iob_rom_atdp/iob_rom_atdp.py
@@ -117,11 +117,16 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
             // Declare the ROM
    reg [DATA_W-1:0] rom[2**ADDR_W-1:0];
 
    // Initialize the ROM
-   initial if ( MEM_INIT_FILE_INT != "none") $readmemh( MEM_INIT_FILE_INT, rom, 0, 2 ** ADDR_W - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh( MEM_INIT_FILE_INT, rom, 0, 2 ** ADDR_W - 1);
+       end
+   endgenerate
 
    always @(posedge clk_a_i)  // Port A
       if (r_en_a_i)

diff --git a/py2hwsw/lib/hardware/memories/rom/iob_rom_sp/iob_rom_sp.py b/py2hwsw/lib/hardware/memories/rom/iob_rom_sp/iob_rom_sp.py
@@ -73,14 +73,19 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
             // Declare the ROM
    reg [DATA_W-1:0] rom[(2**ADDR_W)-1:0];
 
    // Initialize the ROM
-   initial if ( MEM_INIT_FILE_INT != "none") $readmemh( MEM_INIT_FILE_INT, rom, 0, (2 ** ADDR_W) - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh( MEM_INIT_FILE_INT, rom, 0, (2 ** ADDR_W) - 1);
+       end
+   endgenerate
 
    // Operate the ROM
-   always @(posedge clk_i) if (r_en_i) 
+   always @(posedge clk_i) if (r_en_i)
    r_data_o <= rom[addr_i];
             """,
             },

diff --git a/py2hwsw/lib/hardware/memories/rom/iob_rom_tdp/iob_rom_tdp.py b/py2hwsw/lib/hardware/memories/rom/iob_rom_tdp/iob_rom_tdp.py
@@ -110,15 +110,16 @@ def setup(py_params_dict):
         "snippets": [
             {
                 "verilog_code": """
+   localparam INIT_RAM = (MEM_INIT_FILE_INT != "none") ? 1 : 0;
             // Declare the ROM
    reg [DATA_W-1:0] rom[(2**ADDR_W)-1:0];
 
    // Initialize the ROM
-   initial begin
-       if (MEM_INIT_FILE_INT != "none") begin
-           $readmemh(MEM_INIT_FILE_INT, rom, 0, (2 ** ADDR_W) - 1);
+   generate
+       if (INIT_RAM) begin : mem_init
+           initial $readmemh(MEM_INIT_FILE_INT, rom, 0, (2 ** ADDR_W) - 1);
        end
-   end
+   endgenerate
 
    always @(posedge clk_i) begin  // Port A
       if (r_en_a_i) begin