write_verilog: don't emit code with dangling else related to wrong condition #2793
Job | Run time |
---|---|
10m 38s | |
10m 11s | |
10m 6s | |
10m 10s | |
24m 29s | |
9m 35s | |
9m 2s | |
8m 52s | |
10m 5s | |
8m 51s | |
1h 51m 59s |
Job | Run time |
---|---|
10m 38s | |
10m 11s | |
10m 6s | |
10m 10s | |
24m 29s | |
9m 35s | |
9m 2s | |
8m 52s | |
10m 5s | |
8m 51s | |
1h 51m 59s |