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equiv_simple: Drop hollow conditional
All the listed flip-flop types would be known cells, so the extra part of the conditional is without effect.
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It seems like
ct
does not contain these ff cells, see the definition above:Perhaps we also need to add
or it might be better to use
&& ! RTLIL::builtin_ff_cell_types().count(cell->type)
instead, just like in line 63.As I checked, in the current version, all such cells do not appear in the bit2driver.
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But the check that was removed is in negation, so those FF types not being in ct is consistent with the conditional being hollow, no?
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Ah, sorry, wrote too soon, scratch that. I will look into it again later.
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@ArkadyKlimov, by the way, I see you are trying out LEC with Yosys, make sure you look at EQY, which is the recommended tool for that: https://github.com/YosysHQ/eqy
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Better link here: https://yosyshq.readthedocs.io/projects/eqy/en/latest/
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Thanks for the information, I didn't know about that. But why eqy? As far as I could understand, it is just an add-on, a front-end, perhaps more friendly, over yosys itself and, possibly, other tools (SMT solvers, ABC, etc.) But will it really be easier to deal with?
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EQY is meant to be a full-fledged tool that users can use to perform LEC on their designs. It's better maintained, scales better on large designs (due to partitioning), and allows for different proof strategies. It doesn't rely on the
equiv_*
passes which are part of Yosys, those are more of a tool for internal Yosys testing.