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Removed SystemVerilog module end label
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rherveille committed Mar 19, 2024
1 parent 7647eb7 commit 2893938
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions techlibs/intel/max10/cells_sim.v
Original file line number Diff line number Diff line change
Expand Up @@ -322,7 +322,7 @@ module fiftyfivenm_mac_mult (
input aclr;
input clk;
input ena;
endmodule : fiftyfivenm_mac_mult
endmodule //fiftyfivenm_mac_mult

module fiftyfivenm_mac_out (
dataa,
Expand All @@ -342,4 +342,4 @@ module fiftyfivenm_mac_out (
input aclr;
input clk;
input ena;
endmodule : fiftyfivenm_mac_out
endmodule //fiftyfivenm_mac_out

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