Compare with sim -sim-cmp, not vcdiff

backends/functional/cxx.cc

@@ -189,7 +189,7 @@ class CxxComputeGraphFactory {
   T logical_shift_left(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shl), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
   T logical_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($shr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
   T arithmetic_shift_right(T a, T b, int y_width, int) { return graph.add(CxxFunction(ID($asr), y_width, {{ID(WIDTH), y_width}}), 0, std::array<T, 2>{a, b}); }
-  T mul(T a, T b, int width) {return graph.add(CxxFunction(ID($mul), width), 0, std::array<T, 2>{a, b}); }
+  T mul(T a, T b, int width) { return graph.add(CxxFunction(ID($mul), width), 0, std::array<T, 2>{a, b}); }
 
   T constant(RTLIL::Const value) {
     return graph.add(CxxFunction(ID($$const), value.size(), {{ID(value), value}}), 0);

tests/functional/single_bit/run-test.sh

@@ -22,17 +22,15 @@ run_test() {
 
         # Generate VCD files with base_name
         if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd; then
-            # Run vcdiff and capture the output
-            local output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd 2>&1)
-
-            # Check if there is any output
-            if [ -n "$output" ]; then
-                echo "Differences detected in $verilog_file:"
-                echo "$output"
-                failing_files["$verilog_file"]="Differences detected"
-            else
-                echo "No differences detected in $verilog_file."
-            fi
+
+	    # Run yosys to process each Verilog file
+	    if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then
+		echo "Yosys sim $verilog_file successfully."
+	    else
+		echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx"
+		failing_files["$verilog_file"]="Yosys sim failure"
+	    fi
+
         else
             echo "Failed to generate VCD files for $verilog_file."
             failing_files["$verilog_file"]="VCD generation failure"

tests/functional/single_bit/vcd_harness.cpp

@@ -57,6 +57,7 @@ int main(int argc, char **argv)
     std::ofstream vcd_file(functional_vcd_filename);
 
     vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n";
+    vcd_file << "$scope module my_module $end\n";
     {
         DumpHeader d(vcd_file);
         inputs.dump(d);