Add RF initialization

YosysHQ · May 17, 2024 · 2d8287d · 2d8287d
1 parent b1c05b6
commit 2d8287d
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Showing 3 changed files with 29 additions and 5 deletions.
diff --git a/techlibs/nanoxplore/Makefile.inc b/techlibs/nanoxplore/Makefile.inc
@@ -21,6 +21,7 @@ $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_m.v
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/cells_wrap_u.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/io_map.v))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/latches_map.v))
+$(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_init.vh))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_l.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_m.txt))
 $(eval $(call add_share_file,share/nanoxplore,techlibs/nanoxplore/rf_rams_u.txt))

diff --git a/techlibs/nanoxplore/rf_init.vh b/techlibs/nanoxplore/rf_init.vh
@@ -0,0 +1,17 @@
+function [9728-1:0] rf_init_to_string;
+    input [1152-1:0] array;
+    input integer blocks;
+    input integer width;
+    reg [9728-1:0] temp; // (1152+1152/18)*8
+    integer i;
+begin
+    temp = "";
+    for (i = 0; i < blocks; i = i + 1) begin
+    if (i != 0) begin
+        temp = {temp, ","};
+    end
+    temp = {temp, $sformatf("%b",array[(i+1)*width-1: i*width])};
+    end
+    rf_init_to_string = temp;
+end
+endfunction
diff --git a/techlibs/nanoxplore/rf_rams_map_u.v b/techlibs/nanoxplore/rf_rams_map_u.v
@@ -12,13 +12,17 @@ module $__NX_RFB_U_DPREG_ (
   parameter OPTION_MODE = 0;
   parameter WIDTH = 18;
   parameter BITS_USED = 0;
+  localparam BLOCK_NUM  = OPTION_MODE == 2 ? 64 : 32;
+  localparam BLOCK_SIZE = OPTION_MODE == 3 ? 36 : 18;
+
+`include "rf_init.vh"
 
   // mode 0 - DPREG
   // mode 2 - NX_XRFB_64x18
   // mode 3 - NX_XRFB_32x36
   NX_RFB_U #(
     .mode(OPTION_MODE),
-    .mem_ctxt(INIT),
+    .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, BLOCK_NUM, BLOCK_SIZE))),
     .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_W_CLK),
@@ -122,13 +126,14 @@ module $__NX_RFB_U_SPREG_ (
   input PORT_RW_WR_EN,
   output [17:0] PORT_RW_RD_DATA
 );
-  parameter INIT = 1152'bx;
+  parameter INIT = 576'bx;
   parameter PORT_RW_CLK_POL = 1'b1;
   parameter BITS_USED = 0;
+`include "rf_init.vh"
 
   NX_RFB_U #(
     .mode(1),
-    .mem_ctxt(INIT),
+    .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))),
     .wck_edge(PORT_RW_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_RW_CLK),
@@ -235,13 +240,14 @@ module $__NX_XRFB_2R_1W_ (
   output [17:0] PORT_A_RD_DATA,
   output [17:0] PORT_B_RD_DATA
 );
-  parameter INIT = 1152'bx;
+  parameter INIT = 576'bx;
   parameter PORT_W_CLK_POL = 1'b1;
   parameter BITS_USED = 0;
+`include "rf_init.vh"
 
   NX_RFB_U #(
     .mode(4),
-    .mem_ctxt(INIT),
+    .mem_ctxt($sformatf("%s",rf_init_to_string(INIT, 32, 18))),
     .wck_edge(PORT_W_CLK_POL == 1 ? 1'b0 : 1'b1)
   ) _TECHMAP_REPLACE_ (
     .WCK(PORT_W_CLK),