VHDL only build support

Makefile

@@ -20,6 +20,7 @@ ENABLE_VERIFIC := 0
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
 DISABLE_VERIFIC_EXTENSIONS := 0
+DISABLE_VERIFIC_SYSTEMVERILOG := 0
 DISABLE_VERIFIC_VHDL := 0
 DISABLE_VERIFIC_HIER_TREE := 0
 ENABLE_COVER := 1
@@ -472,7 +473,7 @@ endif
 LIBS_VERIFIC =
 ifeq ($(ENABLE_VERIFIC),1)
 VERIFIC_DIR ?= /usr/local/src/verific_lib
-VERIFIC_COMPONENTS ?= verilog database util containers
+VERIFIC_COMPONENTS ?= database util containers
 ifneq ($(DISABLE_VERIFIC_HIER_TREE),1)
 VERIFIC_COMPONENTS += hier_tree
 CXXFLAGS += -DVERIFIC_HIER_TREE_SUPPORT
@@ -481,6 +482,14 @@ ifneq ($(wildcard $(VERIFIC_DIR)/hier_tree),)
 VERIFIC_COMPONENTS += hier_tree
 endif
 endif
+ifneq ($(DISABLE_VERIFIC_SYSTEMVERILOG),1)
+VERIFIC_COMPONENTS += verilog
+CXXFLAGS += -DVERIFIC_SYSTEMVERILOG_SUPPORT
+else
+ifneq ($(wildcard $(VERIFIC_DIR)/verilog),)
+VERIFIC_COMPONENTS += verilog
+endif
+endif
 ifneq ($(DISABLE_VERIFIC_VHDL),1)
 VERIFIC_COMPONENTS += vhdl
 CXXFLAGS += -DVERIFIC_VHDL_SUPPORT