WIP

tests/functional/multi_bit/run-test.sh

@@ -1,38 +1,36 @@
 #!/bin/bash
 
-set -ex
-
-# Define the common variable for the relative path
-BASE_PATH="../../../"
-
 # Initialize an array to store the names of failing Verilog files and their failure types
 declare -A failing_files
 
-# Loop through all Verilog files in the verilog directory
-for verilog_file in verilog/*.v; do
+# Function to run the test on a given Verilog file
+run_test() {
+    # Define the common variable for the relative path
+    BASE_PATH="../../../"
+
+    local verilog_file=$1
+
     # Extract the base name without extension
-    base_name=$(basename "$verilog_file" .v)
+    local base_name=$(basename "$verilog_file" .v)
 
     # Run yosys to process each Verilog file
-    if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_cxxrtl my_module_cxxrtl.cc; write_functional_cxx my_module_functional_cxx.cc"; then
+    if ${BASE_PATH}yosys -p "read_verilog $verilog_file; write_functional_cxx my_module_functional_cxx.cc"; then
         echo "Yosys processed $verilog_file successfully."
 
         # Compile the generated C++ files with vcd_harness.cpp
-        ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cpp -I ${BASE_PATH}backends/functional/cxx_runtime/ -I ${BASE_PATH}backends/cxxrtl/runtime/ -o vcd_harness
+        ${CXX:-g++} -g -fprofile-arcs -ftest-coverage vcd_harness.cc -I ${BASE_PATH}backends/functional/cxx_runtime/ -o vcd_harness
 
         # Generate VCD files with base_name
-        if ./vcd_harness ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd ; then
-            # Run vcdiff and capture the output
-            output=$(vcdiff ${base_name}_functional_cxx.vcd ${base_name}_cxxrtl.vcd)
-
-            # Check if there is any output
-            if [ -n "$output" ]; then
-                echo "Differences detected in $verilog_file:"
-                echo "$output"
-                failing_files["$verilog_file"]="Differences detected"
-            else
-                echo "No differences detected in $verilog_file."
-            fi
+        if ./vcd_harness ${base_name}_functional_cxx.vcd; then
+
+	    # Run yosys to process each Verilog file
+	    if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us -sim-cmp"; then
+		echo "Yosys sim $verilog_file successfully."
+	    else
+		echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx"
+		failing_files["$verilog_file"]="Yosys sim failure"
+	    fi
+
         else
             echo "Failed to generate VCD files for $verilog_file."
             failing_files["$verilog_file"]="VCD generation failure"
@@ -41,16 +39,29 @@ for verilog_file in verilog/*.v; do
         echo "Yosys failed to process $verilog_file."
         failing_files["$verilog_file"]="Yosys failure"
     fi
-done
+}
 
-# Check if the array of failing files is empty
-if [ ${#failing_files[@]} -eq 0 ]; then
-    echo "All files passed."
-    exit 0
-else
-    echo "The following files failed:"
-    for file in "${!failing_files[@]}"; do
-        echo "$file: ${failing_files[$file]}"
+# Main function to run all tests
+run_all_tests() {
+    # Loop through all Verilog files in the verilog directory
+    for verilog_file in verilog/*.v; do
+        run_test "$verilog_file"
     done
-    exit 1
+
+    # Check if the array of failing files is empty
+    if [ ${#failing_files[@]} -eq 0 ]; then
+        echo "All files passed."
+        return 0
+    else
+        echo "The following files failed:"
+        for file in "${!failing_files[@]}"; do
+            echo "$file: ${failing_files[$file]}"
+        done
+        return 1
+    fi
+}
+
+# If the script is being sourced, do not execute the tests
+if [[ "${BASH_SOURCE[0]}" == "${0}" ]]; then
+    run_all_tests
 fi

tests/functional/multi_bit/vcd_harness.cpp → tests/functional/multi_bit/vcd_harness.cc

@@ -3,9 +3,6 @@
 #include <fstream>
 #include <random>
 
-#include <cxxrtl/cxxrtl_vcd.h>
-
-#include "my_module_cxxrtl.cc"
 #include "my_module_functional_cxx.cc"
 
 struct DumpHeader {
@@ -38,13 +35,12 @@ struct Dump {
 
 int main(int argc, char **argv)
 {
-    if (argc != 3) {
-        std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename> <cxxrtl_vcd_filename>\n";
+    if (argc != 2) {
+        std::cerr << "Usage: " << argv[0] << " <functional_vcd_filename>\n";
         return 1;
     }
 
     const std::string functional_vcd_filename = argv[1];
-    const std::string cxxrtl_vcd_filename = argv[2];
 
     constexpr int steps = 10;
     constexpr int number_timescale = 1;
@@ -57,31 +53,14 @@ int main(int argc, char **argv)
     std::ofstream vcd_file(functional_vcd_filename);
 
     vcd_file << "$timescale " << number_timescale << " " << units_timescale << " $end\n";
+    vcd_file << "$scope module my_module $end\n";
     {
         DumpHeader d(vcd_file);
         inputs.dump(d);
         outputs.dump(d);
         state.dump(d);
     }
     vcd_file << "$enddefinitions $end\n$dumpvars\n";
-
-    cxxrtl_design::p_my__module top;
-
-    cxxrtl::debug_items all_debug_items;
-    cxxrtl::debug_scope debug_scope;
-    top.debug_info(&all_debug_items, nullptr, "");
-
-    cxxrtl::vcd_writer vcd;
-    vcd.timescale(number_timescale, units_timescale);
-    vcd.add_without_memories(all_debug_items);
-
-    std::ofstream waves(cxxrtl_vcd_filename);
-
-    top.p_a.set<8>(false);
-    top.p_b.set<8>(false);
-    top.step();
-
-    vcd.sample(0);
     vcd_file << "#0\n";
     inputs.a = $const<8>(false);
     inputs.b = $const<8>(false);
@@ -101,19 +80,10 @@ int main(int argc, char **argv)
         const bool a_value = dist(gen);
         const bool b_value = dist(gen);
 
-        // cxxrtl
-        top.p_a.set<bool>(a_value);
-        top.p_b.set<bool>(b_value);
-        top.step();
-        vcd.sample(step + 1);
-
-        waves << vcd.buffer;
-        vcd.buffer.clear();
-
         // Functional backend cxx
         vcd_file << "#" << (step + 1) << "\n";
-        inputs.a = $const<8>(a_value);
-        inputs.b = $const<8>(b_value);
+        inputs.a = $const<1>(a_value);
+        inputs.b = $const<1>(b_value);
 
         my_module(inputs, outputs, state, next_state);
         {
@@ -127,7 +97,6 @@ int main(int argc, char **argv)
     }
 
     vcd_file.close();
-    waves.close();
 
     return 0;
 }