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Commit 4fbf18b

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mmickommicko
committed
block ram mapping for standard modes
1 parent 2d8287d commit 4fbf18b

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3 files changed

+109
-39
lines changed

3 files changed

+109
-39
lines changed

‎techlibs/nanoxplore/brams.txt

+38-18
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,46 @@
11
ram block $__NX_RAM_ {
2-
abits 13;
3-
widths 1 2 4 9 per_port;
2+
option "STD_MODE" "NOECC_48kx1" {
3+
# only 32k used
4+
abits 15;
5+
widths 1 global;
6+
}
7+
option "STD_MODE" "NOECC_24kx2" {
8+
# only 16k used
9+
abits 14;
10+
widths 2 global;
11+
}
12+
option "STD_MODE" "NOECC_16kx3" {
13+
abits 14;
14+
widths 3 global;
15+
}
16+
option "STD_MODE" "NOECC_12kx4" {
17+
# only 8k used
18+
abits 13;
19+
widths 4 global;
20+
}
21+
option "STD_MODE" "NOECC_8kx6" {
22+
abits 13;
23+
widths 6 global;
24+
}
25+
option "STD_MODE" "NOECC_6kx8" {
26+
# only 4k used
27+
abits 12;
28+
widths 8 global;
29+
}
30+
option "STD_MODE" "NOECC_4kx12" {
31+
abits 12;
32+
widths 12 global;
33+
}
34+
option "STD_MODE" "NOECC_2kx24" {
35+
abits 11;
36+
widths 24 global;
37+
}
438
cost 64;
539
init no_undef;
640
port srsw "A" "B" {
741
clock anyedge;
842
clken;
9-
portoption "WRITEMODE" "NORMAL" {
10-
rdwr no_change;
11-
}
12-
portoption "WRITEMODE" "WRITETHROUGH" {
13-
rdwr new;
14-
}
15-
portoption "WRITEMODE" "READBEFOREWRITE" {
16-
rdwr old;
17-
}
18-
option "RESETMODE" "SYNC" {
19-
rdsrst zero ungated block_wr;
20-
}
21-
option "RESETMODE" "ASYNC" {
22-
rdarst zero;
23-
}
24-
rdinit zero;
43+
rdwr no_change;
44+
rdinit none;
2545
}
2646
}

‎techlibs/nanoxplore/brams_map.v

+67-17
Original file line numberDiff line numberDiff line change
@@ -1,43 +1,93 @@
11
module $__NX_RAM_ (...);
22

33
parameter INIT = 0;
4-
parameter OPTION_RESETMODE = "SYNC";
4+
parameter OPTION_STD_MODE = "";
55

6-
parameter PORT_A_WIDTH = 9;
6+
parameter WIDTH = 24;
77
parameter PORT_A_CLK_POL = 1;
8-
parameter PORT_A_OPTION_WRITEMODE = "NORMAL";
98

109
input PORT_A_CLK;
1110
input PORT_A_CLK_EN;
1211
input PORT_A_WR_EN;
13-
input PORT_A_RD_SRST;
14-
input PORT_A_RD_ARST;
15-
input [12:0] PORT_A_ADDR;
16-
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
17-
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
12+
input [15:0] PORT_A_ADDR;
13+
input [WIDTH-1:0] PORT_A_WR_DATA;
14+
wire [24-1:0] A_DATA;
15+
output [WIDTH-1:0] PORT_A_RD_DATA;
1816

19-
parameter PORT_B_WIDTH = 9;
2017
parameter PORT_B_CLK_POL = 1;
21-
parameter PORT_B_OPTION_WRITEMODE = "NORMAL";
2218

2319
input PORT_B_CLK;
2420
input PORT_B_CLK_EN;
2521
input PORT_B_WR_EN;
26-
input PORT_B_RD_SRST;
27-
input PORT_B_RD_ARST;
28-
input [12:0] PORT_B_ADDR;
29-
input [PORT_B_WIDTH-1:0] PORT_B_WR_DATA;
30-
output [PORT_B_WIDTH-1:0] PORT_B_RD_DATA;
22+
input [15:0] PORT_B_ADDR;
23+
input [WIDTH-1:0] PORT_B_WR_DATA;
24+
wire [24-1:0] B_DATA;
25+
output [WIDTH-1:0] PORT_B_RD_DATA;
26+
27+
generate
28+
if (OPTION_STD_MODE == "NOECC_48kx1") begin
29+
assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
30+
assign B_DATA = {24{PORT_B_WR_DATA[WIDTH-1:0]}};
31+
end
32+
else if (OPTION_STD_MODE == "NOECC_24kx2") begin
33+
assign A_DATA = {12{PORT_A_WR_DATA[WIDTH-1:0]}};
34+
assign B_DATA = {12{PORT_B_WR_DATA[WIDTH-1:0]}};
35+
end
36+
else if (OPTION_STD_MODE == "NOECC_16kx3") begin
37+
assign A_DATA = {8{PORT_A_WR_DATA[WIDTH-1:0]}};
38+
assign B_DATA = {8{PORT_B_WR_DATA[WIDTH-1:0]}};
39+
end
40+
else if (OPTION_STD_MODE == "NOECC_12kx4") begin
41+
assign A_DATA = {6{PORT_A_WR_DATA[WIDTH-1:0]}};
42+
assign B_DATA = {6{PORT_B_WR_DATA[WIDTH-1:0]}};
43+
end
44+
else if (OPTION_STD_MODE == "NOECC_8kx6") begin
45+
assign A_DATA = {4{PORT_A_WR_DATA[WIDTH-1:0]}};
46+
assign B_DATA = {4{PORT_B_WR_DATA[WIDTH-1:0]}};
47+
end
48+
else if (OPTION_STD_MODE == "NOECC_6kx8") begin
49+
assign A_DATA = {3{PORT_A_WR_DATA[WIDTH-1:0]}};
50+
assign B_DATA = {3{PORT_B_WR_DATA[WIDTH-1:0]}};
51+
end
52+
else if (OPTION_STD_MODE == "NOECC_4kx12") begin
53+
assign A_DATA = {2{PORT_A_WR_DATA[WIDTH-1:0]}};
54+
assign B_DATA = {2{PORT_B_WR_DATA[WIDTH-1:0]}};
55+
end
56+
else if (OPTION_STD_MODE == "NOECC_2kx24") begin
57+
assign A_DATA = PORT_A_WR_DATA;
58+
assign B_DATA = PORT_B_WR_DATA;
59+
end
60+
endgenerate
3161

3262
NX_RAM_WRAP #(
63+
.std_mode(OPTION_STD_MODE),
64+
.mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
65+
.mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
3366
) _TECHMAP_REPLACE_ (
3467
.ACK(PORT_A_CLK),
68+
//.ACKS(PORT_A_CLK),
69+
//.ACKD(), // Not used in Non-ECC modes
70+
//.ACKR(),
71+
//.AR(),
72+
//.ACOR(),
73+
//.AERR(),
74+
.ACS(PORT_A_CLK_EN),
75+
.AWE(PORT_A_WR_EN),
76+
3577
.AA(PORT_A_ADDR),
36-
.AI(PORT_A_WR_DATA),
78+
.AI(A_DATA),
3779
.AO(PORT_A_RD_DATA),
3880

3981
.BCK(PORT_B_CLK),
40-
.BA(PORT_B_ADDR),
82+
//.BCKC(PORT_B_CLK),
83+
//.BCKD(), // Not used in Non-ECC modes
84+
//.BCKR()
85+
//.BR(),
86+
//.BCOR(),
87+
//.BERR(),
88+
.BCS(PORT_B_CLK_EN),
89+
.BWE(PORT_B_WR_EN),
90+
.BA(B_DATA),
4191
.BI(PORT_B_WR_DATA),
4292
.BO(PORT_B_RD_DATA)
4393
);

‎techlibs/nanoxplore/cells_bb.v

+4-4
Original file line numberDiff line numberDiff line change
@@ -255,10 +255,10 @@ module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4,
255255
parameter pipe_ob = 1'b0;
256256
parameter raw_config0 = 4'b0000;
257257
parameter raw_config1 = 16'b0000000000000000;
258-
parameter raw_l_enable = 1'b0;
259-
parameter raw_l_extend = 4'b0000;
260-
parameter raw_u_enable = 1'b0;
261-
parameter raw_u_extend = 8'b00000000;
258+
//parameter raw_l_enable = 1'b0;
259+
//parameter raw_l_extend = 4'b0000;
260+
//parameter raw_u_enable = 1'b0;
261+
//parameter raw_u_extend = 8'b00000000;
262262
parameter std_mode = "";
263263
endmodule
264264

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