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Remove coverage
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@RCoeurjoly
RCoeurjoly committed May 31, 2024
1 parent b8dc9c5 commit 54536af
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204 changes: 204 additions & 0 deletions dsn
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#! /nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/bin/vvp
:ivl_version "12.0 (stable)";
:ivl_delay_selection "TYPICAL";
:vpi_time_precision + 0;
:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/system.vpi";
:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/vhdl_sys.vpi";
:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/vhdl_textio.vpi";
:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/v2005_math.vpi";
:vpi_module "/nix/store/7f3kcbzgv0m5nk1z24lg38127yg4r90k-iverilog-12.0/lib/ivl/va_math.vpi";
S_0x703640 .scope module, "testbench" "testbench" 2 4;
.timescale 0 0;
v0x74c7f0_0 .var/i "file", 31 0;
v0x74c8d0_0 .var "filename", 1023 0;
v0x74c9b0_0 .var/i "i", 31 0;
v0x74ca70_0 .var "sig_my_module_a", 0 0;
v0x74cb60_0 .var "sig_my_module_b", 0 0;
v0x74cc50_0 .net "sig_my_module_y", 0 0, L_0x74d160; 1 drivers
v0x74cd20_0 .var "xorshift128_t", 31 0;
v0x74cde0_0 .var "xorshift128_w", 31 0;
v0x74cec0_0 .var "xorshift128_x", 31 0;
v0x74cfa0_0 .var "xorshift128_y", 31 0;
v0x74d080_0 .var "xorshift128_z", 31 0;
S_0x6efef0 .scope task, "my_module_print_header" "my_module_print_header" 2 69, 2 69 0, S_0x703640;
.timescale 0 0;
TD_testbench.my_module_print_header ;
%vpi_call 2 71 "$fdisplay", v0x74c7f0_0, "#OUT#" {0 0 0};
%vpi_call 2 72 "$fdisplay", v0x74c7f0_0, "#OUT# A sig_my_module_a" {0 0 0};
%vpi_call 2 73 "$fdisplay", v0x74c7f0_0, "#OUT# B sig_my_module_b" {0 0 0};
%vpi_call 2 74 "$fdisplay", v0x74c7f0_0, "#OUT# C sig_my_module_y" {0 0 0};
%vpi_call 2 75 "$fdisplay", v0x74c7f0_0, "#OUT#" {0 0 0};
%vpi_call 2 76 "$fdisplay", v0x74c7f0_0, "#OUT# AB # C" {0 0 0};
%end;
S_0x701c90 .scope task, "my_module_print_status" "my_module_print_status" 2 63, 2 63 0, S_0x703640;
.timescale 0 0;
TD_testbench.my_module_print_status ;
%load/vec4 v0x74ca70_0;
%load/vec4 v0x74cb60_0;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x74cc50_0;
%vpi_call 2 65 "$fdisplay", v0x74c7f0_0, "#OUT# %b %b %b %t %d", S<1,vec4,u2>, 1'bx, S<0,vec4,u1>, $time, v0x74c9b0_0 {2 0 0};
%end;
S_0x701e70 .scope task, "my_module_reset" "my_module_reset" 2 36, 2 36 0, S_0x703640;
.timescale 0 0;
TD_testbench.my_module_reset ;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x74ca70_0, 2;
%pushi/vec4 0, 0, 1;
%assign/vec4 v0x74cb60_0, 4;
%delay 100, 0;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x74ca70_0, 2;
%pushi/vec4 1, 0, 1;
%assign/vec4 v0x74cb60_0, 4;
%delay 100, 0;
%delay 0, 0;
%end;
S_0x733630 .scope task, "my_module_test" "my_module_test" 2 80, 2 80 0, S_0x703640;
.timescale 0 0;
TD_testbench.my_module_test ;
%vpi_call 2 82 "$fdisplay", v0x74c7f0_0, "#OUT#\012#OUT# ==== my_module ====" {0 0 0};
%fork TD_testbench.my_module_reset, S_0x701e70;
%join;
%pushi/vec4 0, 0, 32;
%store/vec4 v0x74c9b0_0, 0, 32;
T_3.0 ;
%load/vec4 v0x74c9b0_0;
%cmpi/s 1000, 0, 32;
%jmp/0xz T_3.1, 5;
%load/vec4 v0x74c9b0_0;
%pushi/vec4 20, 0, 32;
%mod/s;
%cmpi/e 0, 0, 32;
%jmp/0xz T_3.2, 4;
%fork TD_testbench.my_module_print_header, S_0x6efef0;
%join;
T_3.2 ;
%delay 100, 0;
%fork TD_testbench.my_module_update_data, S_0x71fde0;
%join;
%delay 100, 0;
%fork TD_testbench.my_module_update_clock, S_0x733810;
%join;
%delay 100, 0;
%fork TD_testbench.my_module_print_status, S_0x701c90;
%join;
%load/vec4 v0x74c9b0_0;
%addi 1, 0, 32;
%store/vec4 v0x74c9b0_0, 0, 32;
%jmp T_3.0;
T_3.1 ;
%end;
S_0x733810 .scope task, "my_module_update_clock" "my_module_update_clock" 2 58, 2 58 0, S_0x703640;
.timescale 0 0;
TD_testbench.my_module_update_clock ;
%end;
S_0x71fde0 .scope task, "my_module_update_data" "my_module_update_data" 2 48, 2 48 0, S_0x703640;
.timescale 0 0;
TD_testbench.my_module_update_data ;
%fork TD_testbench.xorshift128, S_0x74c610;
%join;
%load/vec4 v0x74cec0_0;
%load/vec4 v0x74cfa0_0;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x74d080_0;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x74cde0_0;
%concat/vec4; draw_concat_vec4
%pad/u 1;
%assign/vec4 v0x74ca70_0, 2;
%fork TD_testbench.xorshift128, S_0x74c610;
%join;
%load/vec4 v0x74cec0_0;
%load/vec4 v0x74cfa0_0;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x74d080_0;
%concat/vec4; draw_concat_vec4
%load/vec4 v0x74cde0_0;
%concat/vec4; draw_concat_vec4
%pad/u 1;
%assign/vec4 v0x74cb60_0, 4;
%delay 100, 0;
%end;
S_0x71ffc0 .scope module, "uut_my_module" "my_module" 2 30, 3 1 0, S_0x703640;
.timescale 0 0;
.port_info 0 /INPUT 1 "a";
.port_info 1 /INPUT 1 "b";
.port_info 2 /OUTPUT 1 "y";
L_0x74d160 .functor AND 1, v0x74ca70_0, v0x74cb60_0, C4<1>, C4<1>;
v0x7201f0_0 .net "a", 0 0, v0x74ca70_0; 1 drivers
v0x74c430_0 .net "b", 0 0, v0x74cb60_0; 1 drivers
v0x74c4f0_0 .net "y", 0 0, L_0x74d160; alias, 1 drivers
S_0x74c610 .scope task, "xorshift128" "xorshift128" 2 17, 2 17 0, S_0x703640;
.timescale 0 0;
TD_testbench.xorshift128 ;
%load/vec4 v0x74cec0_0;
%load/vec4 v0x74cec0_0;
%ix/load 4, 11, 0;
%flag_set/imm 4, 0;
%shiftl 4;
%xor;
%store/vec4 v0x74cd20_0, 0, 32;
%load/vec4 v0x74cfa0_0;
%store/vec4 v0x74cec0_0, 0, 32;
%load/vec4 v0x74d080_0;
%store/vec4 v0x74cfa0_0, 0, 32;
%load/vec4 v0x74cde0_0;
%store/vec4 v0x74d080_0, 0, 32;
%load/vec4 v0x74cde0_0;
%load/vec4 v0x74cde0_0;
%ix/load 4, 19, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%xor;
%load/vec4 v0x74cd20_0;
%xor;
%load/vec4 v0x74cd20_0;
%ix/load 4, 8, 0;
%flag_set/imm 4, 0;
%shiftr 4;
%xor;
%store/vec4 v0x74cde0_0, 0, 32;
%end;
.scope S_0x703640;
T_7 ;
%pushi/vec4 123456789, 0, 32;
%store/vec4 v0x74cec0_0, 0, 32;
%pushi/vec4 362436069, 0, 32;
%store/vec4 v0x74cfa0_0, 0, 32;
%pushi/vec4 521288629, 0, 32;
%store/vec4 v0x74d080_0, 0, 32;
%pushi/vec4 1716911459, 0, 32;
%store/vec4 v0x74cde0_0, 0, 32;
%end;
.thread T_7;
.scope S_0x703640;
T_8 ;
%vpi_func 2 94 "$value$plusargs" 32, "VCD=%s", v0x74c8d0_0 {0 0 0};
%cmpi/ne 0, 0, 32;
%jmp/0xz T_8.0, 4;
%vpi_call 2 95 "$dumpfile", v0x74c8d0_0 {0 0 0};
%vpi_call 2 96 "$dumpvars", 32'sb00000000000000000000000000000000, S_0x703640 {0 0 0};
T_8.0 ;
%vpi_func 2 98 "$value$plusargs" 32, "OUT=%s", v0x74c8d0_0 {0 0 0};
%cmpi/ne 0, 0, 32;
%jmp/0xz T_8.2, 4;
%vpi_func 2 99 "$fopen" 32, v0x74c8d0_0 {0 0 0};
%store/vec4 v0x74c7f0_0, 0, 32;
%jmp T_8.3;
T_8.2 ;
%vpi_func 2 101 "$fopen" 32, "/dev/stdout" {0 0 0};
%store/vec4 v0x74c7f0_0, 0, 32;
T_8.3 ;
%fork TD_testbench.my_module_test, S_0x733630;
%join;
%vpi_call 2 104 "$fclose", v0x74c7f0_0 {0 0 0};
%vpi_call 2 105 "$finish" {0 0 0};
%end;
.thread T_8;
# The file index is used to find the file name in the following table.
:file_names 4;
"N/A";
"<interactive>";
"test_and.v";
"tests/functional/single_bit/verilog/my_module_and.v";
2 changes: 1 addition & 1 deletion flake.nix
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Expand Up @@ -66,7 +66,7 @@
defaultPackage = yosys;
packages.vcdiff = vcdiff;
devShell = pkgs.mkShell {
buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov ];
buildInputs = with pkgs; [ clang bison flex libffi tcl readline python3 llvmPackages.libcxxClang zlib git gtest abc-verifier gtkwave vcdiff lcov racket verilog ];
};
}
);
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0 ...nctional/coverage_report/vcd_harness.info → sim.vcd
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108 changes: 108 additions & 0 deletions test_and.v
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`ifndef outfile
`define outfile "/dev/stdout"
`endif
module testbench;

integer i;
integer file;

reg [1023:0] filename;

reg [31:0] xorshift128_x = 123456789;
reg [31:0] xorshift128_y = 362436069;
reg [31:0] xorshift128_z = 521288629;
reg [31:0] xorshift128_w = 1716918015; // <-- seed value
reg [31:0] xorshift128_t;

task xorshift128;
begin
xorshift128_t = xorshift128_x ^ (xorshift128_x << 11);
xorshift128_x = xorshift128_y;
xorshift128_y = xorshift128_z;
xorshift128_z = xorshift128_w;
xorshift128_w = xorshift128_w ^ (xorshift128_w >> 19) ^ xorshift128_t ^ (xorshift128_t >> 8);
end
endtask

wire [0:0] sig_my_module_y;
reg [0:0] sig_my_module_b;
reg [0:0] sig_my_module_a;
my_module uut_my_module(
.y(sig_my_module_y),
.b(sig_my_module_b),
.a(sig_my_module_a)
);

task my_module_reset;
begin
sig_my_module_a <= #2 0;
sig_my_module_b <= #4 0;
#100;
sig_my_module_a <= #2 ~0;
sig_my_module_b <= #4 ~0;
#100;
#0;
end
endtask

task my_module_update_data;
begin
xorshift128;
sig_my_module_a <= #2 { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };
xorshift128;
sig_my_module_b <= #4 { xorshift128_x, xorshift128_y, xorshift128_z, xorshift128_w };
#100;
end
endtask

task my_module_update_clock;
begin
end
endtask

task my_module_print_status;
begin
$fdisplay(file, "#OUT# %b %b %b %t %d", { sig_my_module_a, sig_my_module_b }, { 1'bx }, { sig_my_module_y }, $time, i);
end
endtask

task my_module_print_header;
begin
$fdisplay(file, "#OUT#");
$fdisplay(file, "#OUT# A sig_my_module_a");
$fdisplay(file, "#OUT# B sig_my_module_b");
$fdisplay(file, "#OUT# C sig_my_module_y");
$fdisplay(file, "#OUT#");
$fdisplay(file, {"#OUT# ", "A", "B", " ", "#", " ", "C"});
end
endtask

task my_module_test;
begin
$fdisplay(file, "#OUT#\n#OUT# ==== my_module ====");
my_module_reset;
for (i=0; i<1000; i=i+1) begin
if (i % 20 == 0) my_module_print_header;
#100; my_module_update_data;
#100; my_module_update_clock;
#100; my_module_print_status;
end
end
endtask

initial begin
if ($value$plusargs("VCD=%s", filename)) begin
$dumpfile(filename);
$dumpvars(0, testbench);
end
if ($value$plusargs("OUT=%s", filename)) begin
file = $fopen(filename);
end else begin
file = $fopen(`outfile);
end
my_module_test;
$fclose(file);
$finish;
end

endmodule
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