chore: fix master branch refs

Signed-off-by: Rui Chen <[email protected]>

.github/ISSUE_TEMPLATE/bug_report.yml

@@ -43,7 +43,7 @@ body:
     attributes:
       value: >
         When providing steps to reproduce the issue, please ensure that the issue
-        is reproducible in the current git master of Yosys. Also ensure to
+        is reproducible in the current git main of Yosys. Also ensure to
         provide all necessary source files needed.
 
 

.github/workflows/test-docs.yml

@@ -3,7 +3,7 @@ name: Build and test doc code samples
 on:
   pull_request:
     branches:
-    - master
+    - main
 
 jobs:
   test-docs:

backends/jny/jny.cc

@@ -124,7 +124,7 @@ struct JnyWriter
         design->sort();
 
         f << "{\n";
-        f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json\",\n";
+        f << "  \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n";
         f << stringf("  \"generator\": \"%s\",\n", escape_string(yosys_version_str).c_str());
         f << "  \"version\": \"0.0.1\",\n";
         f << "  \"invocation\": \"" << escape_string(invk) << "\",\n";
@@ -426,7 +426,7 @@ struct JnyBackend : public Backend {
         log("        Don't include property information in the netlist output.\n");
         log("\n");
         log("The JSON schema for JNY output files is located in the \"jny.schema.json\" file\n");
-        log("which is located at \"https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json\"\n");
+        log("which is located at \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\"\n");
         log("\n");
     }
 

docs/source/getting_started/example_synth.rst

@@ -193,7 +193,7 @@ on opt_expr <adv_opt_expr>`.
 .. todo:: consider a brief glossary for terms like adff
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/proc`
    - :doc:`/using_yosys/synthesis/opt`
 
@@ -313,7 +313,7 @@ and merged with the ``raddr`` wire feeding into the ``$memrd`` cell.  This wire
 merging happened during the call to :cmd:ref:`clean` which we can see in the
 :ref:`flat_clean`.
 
-.. note:: 
+.. note::
 
    :cmd:ref:`flatten` and :cmd:ref:`clean` would normally be combined into a
    single :yoterm:`yosys> flatten;;` output, but they appear separately here as
@@ -391,7 +391,7 @@ options is able to fold one of the ``$mux`` cells into the ``$adff`` to form an
    ``rdata`` output after :cmd:ref:`opt_dff`
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/fsm`
    - :doc:`/using_yosys/synthesis/opt`
 
@@ -458,7 +458,7 @@ memory read with appropriate enable (``EN=1'1``) and reset (``ARST=1'0`` and
 ``SRST=1'0``) inputs.
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/opt`
    - :doc:`/using_yosys/synthesis/techmap_synth`
    - :doc:`/using_yosys/synthesis/memory`
@@ -633,9 +633,9 @@ with the mapping to ``SB_RAM40_4K`` done by :cmd:ref:`techmap` using
 into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`.
 
 .. |techlibs/ice40/brams.txt| replace:: :file:`techlibs/ice40/brams.txt`
-.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/master/techlibs/ice40/brams.txt
+.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams.txt
 .. |techlibs/ice40/brams_map.v| replace:: :file:`techlibs/ice40/brams_map.v`
-.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/master/techlibs/ice40/brams_map.v
+.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams_map.v
 
 .. literalinclude:: /cmd/synth_ice40.rst
    :language: yoscrypt
@@ -660,7 +660,7 @@ into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`.
    complex.
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/techmap_synth`
    - :doc:`/using_yosys/synthesis/memory`
 
@@ -760,7 +760,7 @@ Finally we use :cmd:ref:`techmap` to map the generic ``$lut`` cells to iCE40
    ``rdata`` output after :ref:`map_cells`
 
 .. seealso:: Advanced usage docs for
-   
+
    - :doc:`/using_yosys/synthesis/techmap_synth`
    - :doc:`/using_yosys/synthesis/abc`
 

docs/source/test_suites.rst

@@ -16,8 +16,8 @@ Automatic testing
 
 .. _Yosys Git repo: https://github.com/YosysHQ/yosys
 
-.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=master
-.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=master
+.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=main
+.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=main
 
 For up to date information, including OS versions, refer to `the git actions
 page`_.

docs/source/using_yosys/more_scripting/interactive_investigation.rst

@@ -18,7 +18,7 @@ in the circuit diagrams generated by it. The code used is included in the Yosys
 code base under |code_examples/show|_.
 
 .. |code_examples/show| replace:: :file:`docs/source/code_examples/show`
-.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/show
+.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show
 
 A simple circuit
 ^^^^^^^^^^^^^^^^
@@ -57,7 +57,7 @@ is shown.
 
 .. figure:: /_images/code_examples/show/example_first.*
    :class: width-helper
-   
+
    Output of the first :cmd:ref:`show` command in :numref:`example_ys`
 
 The first output shows the design directly after being read by the Verilog
@@ -89,7 +89,7 @@ multiplexer and a d-type flip-flop, which brings us to the second diagram:
 
 .. figure:: /_images/code_examples/show/example_second.*
    :class: width-helper
-   
+
    Output of the second :cmd:ref:`show` command in :numref:`example_ys`
 
 The Rhombus shape to the right is a dangling wire. (Wire nodes are only shown if
@@ -107,14 +107,14 @@ artefacts left behind some operations, it is therefore recommended to always
 call :cmd:ref:`clean` before calling :cmd:ref:`show`.
 
 In this script we directly call :cmd:ref:`opt` as the next step, which finally
-leads us to the third diagram: 
+leads us to the third diagram:
 
 .. figure:: /_images/code_examples/show/example_third.*
    :class: width-helper
    :name: example_out
-   
+
    Output of the third :cmd:ref:`show` command in :ref:`example_ys`
-   
+
 Here we see that the :cmd:ref:`proc` command not only has removed the artifacts
 left behind by :cmd:ref:`proc`, but also determined correctly that it can remove
 the first ``$mux`` cell without changing the behavior of the circuit.
@@ -168,7 +168,7 @@ mapped to a cell library:
    :class: width-helper
    :name: first_pitfall
 
-   A half-adder built from simple CMOS gates, demonstrating common pitfalls when 
+   A half-adder built from simple CMOS gates, demonstrating common pitfalls when
    using :cmd:ref:`show`
 
 .. literalinclude:: /code_examples/show/cmos.ys
@@ -177,7 +177,7 @@ mapped to a cell library:
    :end-at: cmos_00
    :name: pitfall_code
    :caption: Generating :numref:`first_pitfall`
-   
+
 First, Yosys did not have access to the cell library when this diagram was
 generated, resulting in all cell ports defaulting to being inputs. This is why
 all ports are drawn on the left side the cells are awkwardly arranged in a large
@@ -188,7 +188,7 @@ individual bits, resulting in an unnecessary complex diagram.
    :class: width-helper
    :name: second_pitfall
 
-   Effects of :cmd:ref:`splitnets` command and of providing a cell library on 
+   Effects of :cmd:ref:`splitnets` command and of providing a cell library on
    design in :numref:`first_pitfall`
 
 .. literalinclude:: /code_examples/show/cmos.ys
@@ -249,7 +249,7 @@ reproduced. So if, for example, the internal state before calling the
 the coarse-grain version of the circuit before :cmd:ref:`techmap` than the
 gate-level circuit after :cmd:ref:`techmap`.
 
-.. Note:: 
+.. Note::
 
    It is generally recommended to verify the internal state of a design by
    writing it to a Verilog file using :yoscrypt:`write_verilog -noexpr` and
@@ -332,12 +332,12 @@ tools).
 - :doc:`/cmd/dump`.
 - :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a
   design dynamically.
-  
+
 The code used is included in the Yosys code base under
 |code_examples/scrambler|_.
 
 .. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler`
-.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/scrambler
+.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/scrambler
 
 Changing design hierarchy
 ^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -443,7 +443,7 @@ Recall the ``memdemo`` design from :ref:`advanced_logic_cones`:
 
 .. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper
-   
+
    ``memdemo``
 
 Because this produces a rather large circuit, it can be useful to split it into
@@ -464,18 +464,18 @@ below.
 
 .. figure:: /_images/code_examples/selections/submod_02.*
    :class: width-helper
-   
+
    ``outstage``
 
 .. figure:: /_images/code_examples/selections/submod_03.*
    :class: width-helper
    :name: selstage
-   
+
    ``selstage``
 
 .. figure:: /_images/code_examples/selections/submod_01.*
    :class: width-helper
-   
+
    ``scramble``
 
 Evaluation of combinatorial circuits
@@ -546,9 +546,9 @@ larger circuits however, Yosys provides the :cmd:ref:`sat` command that uses a
 
 .. _MiniSAT: http://minisat.se/
 
-.. note:: 
-    
-    While it is possible to perform model checking directly in Yosys, it 
+.. note::
+
+    While it is possible to perform model checking directly in Yosys, it
     is highly recommended to use SBY or EQY for formal hardware verification.
 
 The :cmd:ref:`sat` command works very similar to the :cmd:ref:`eval` command.

docs/source/using_yosys/more_scripting/model_checking.rst

@@ -3,9 +3,9 @@ Symbolic model checking
 
 .. todo:: check text context
 
-.. note:: 
-    
-    While it is possible to perform model checking directly in Yosys, it 
+.. note::
+
+    While it is possible to perform model checking directly in Yosys, it
     is highly recommended to use SBY or EQY for formal hardware verification.
 
 Symbolic Model Checking (SMC) is used to formally prove that a circuit has (or
@@ -29,7 +29,7 @@ Let's take a look at an example included in the Yosys code base under
 |code_examples/synth_flow|_:
 
 .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow`
-.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow
+.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow
 
 .. literalinclude:: /code_examples/synth_flow/techmap_01_map.v
    :language: verilog
@@ -81,7 +81,7 @@ The code used in this section is included in the Yosys code base under
 |code_examples/axis|_.
 
 .. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis`
-.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/axis
+.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis
 
 The following AXI4 Stream Master has a bug. But the bug is not exposed if the
 slave keeps ``tready`` asserted all the time. (Something a test bench might do.)

docs/source/using_yosys/more_scripting/selections.rst

@@ -35,8 +35,8 @@ selection; while :yoscrypt:`delete foobar` will only delete the module foobar.
 If no :cmd:ref:`select` command has been made, then the "current selection" will
 be the whole design.
 
-.. note:: Many of the examples on this page make use of the :cmd:ref:`show` 
-   command to visually demonstrate the effect of selections.  For a more 
+.. note:: Many of the examples on this page make use of the :cmd:ref:`show`
+   command to visually demonstrate the effect of selections.  For a more
    detailed look at this command, refer to :ref:`interactive_show`.
 
 How to make a selection
@@ -106,7 +106,7 @@ at first glance. When it is called with multiple arguments, each argument is
 evaluated and pushed separately on a stack. After all arguments have been
 processed it simply creates the union of all elements on the stack. So
 :yoscrypt:`select t:$add a:foo` will select all ``$add`` cells and all objects
-with the ``foo`` attribute set:   
+with the ``foo`` attribute set:
 
 .. literalinclude:: /code_examples/selections/foobaraddsub.v
    :caption: Test module for operations on selections
@@ -130,7 +130,7 @@ select all ``$add`` cells that have the ``foo`` attribute set:
 
 .. code-block::
    :caption: Output for command ``select t:$add a:foo %i -list`` on :numref:`foobaraddsub`
-   
+
    yosys> select t:$add a:foo %i -list
    foobaraddsub/$add$foobaraddsub.v:4$1
 
@@ -282,7 +282,7 @@ diagram in :numref:`memdemo_00`.
 .. figure:: /_images/code_examples/selections/memdemo_00.*
    :class: width-helper
    :name: memdemo_00
-   
+
    Complete circuit diagram for the design shown in :numref:`memdemo_src`
 
 There's a lot going on there, but maybe we are only interested in the tree of
@@ -293,7 +293,7 @@ cones`_ from above, we can use :yoscrypt:`show y %ci2`:
 .. figure:: /_images/code_examples/selections/memdemo_01.*
    :class: width-helper
    :name: memdemo_01
-   
+
    Output of :yoscrypt:`show y %ci2`
 
 From this we would learn that ``y`` is driven by a ``$dff cell``, that ``y`` is
@@ -305,7 +305,7 @@ start of the name).  Let's go a bit further now and try :yoscrypt:`show y %ci5`:
 .. figure:: /_images/code_examples/selections/memdemo_02.*
    :class: width-helper
    :name: memdemo_02
-   
+
    Output of :yoscrypt:`show y %ci5`
 
 That's starting to get a bit messy, so maybe we want to ignore the mux select
@@ -319,7 +319,7 @@ type with :yoscrypt:`show y %ci5:-$mux[S]`:
 .. figure:: /_images/code_examples/selections/memdemo_03.*
    :class: width-helper
    :name: memdemo_03
-   
+
    Output of :yoscrypt:`show y %ci5:-$mux[S]`
 
 We could use a command such as :yoscrypt:`show y %ci2:+$dff[Q,D]
@@ -330,7 +330,7 @@ multiplexer select inputs and flip-flop cells:
 .. figure:: /_images/code_examples/selections/memdemo_05.*
    :class: width-helper
    :name: memdemo_05
-   
+
    Output of ``show y %ci2:+$dff[Q,D] %ci*:-$mux[S]:-$dff``
 
 Or we could use :yoscrypt:`show y %ci*:-[CLK,S]:+$dff:+$mux` instead, following
@@ -342,7 +342,7 @@ ignoring any ports named ``CLK`` or ``S``:
 .. figure:: /_images/code_examples/selections/memdemo_04.*
    :class: width-helper
    :name: memdemo_04
-   
+
    Output of :yoscrypt:`show y %ci*:-[CLK,S]:+$dff,$mux`
 
 Similar to ``%ci`` exists an action ``%co`` to select output cones that accepts
@@ -405,7 +405,7 @@ those cases selection variables must be used to capture more complex selections.
 Example code from |code_examples/selections|_:
 
 .. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections`
-.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/selections
+.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/selections
 
 .. literalinclude:: /code_examples/selections/select.v
    :language: verilog

docs/source/using_yosys/synthesis/cell_libs.rst

@@ -18,10 +18,10 @@ detail in the :doc:`/getting_started/example_synth` document.
    The :file:`counter.ys` script includes the commands used to generate the
    images in this document.  Code snippets in this document skip these commands;
    including line numbers to allow the reader to follow along with the source.
-   
+
    To learn more about these commands, check out :ref:`interactive_show`.
 
-.. _example project: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/intro
+.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro
 
 A simple counter
 ~~~~~~~~~~~~~~~~
@@ -37,7 +37,7 @@ First, let's quickly look at the design:
 This is a simple counter with reset and enable.  If the reset signal, ``rst``,
 is high then the counter will reset to 0.  Otherwise, if the enable signal,
 ``en``, is high then the ``count`` register will increment by 1 each rising edge
-of the clock, ``clk``.  
+of the clock, ``clk``.
 
 Loading the design
 ~~~~~~~~~~~~~~~~~~