clockgate: bail on constant signals

YosysHQ · Sep 9, 2024 · 7e47329 · 7e47329
1 parent dc039d8
commit 7e47329
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Showing 2 changed files with 48 additions and 1 deletion.
diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc
@@ -151,7 +151,8 @@ struct ClockgatePass : public Pass {
 					continue;
 
 				FfData ff(&initvals, cell);
-				if (ff.has_ce) {
+				// It would be odd to get constants, but we better handle it
+				if (ff.has_ce && ff.sig_clk.is_wire() && ff.sig_ce.is_wire()) {
 					ce_ffs.insert(cell);
 
 					ClkNetInfo info = clk_info_from_ff(ff);

diff --git a/tests/techmap/clockgate.ys b/tests/techmap/clockgate.ys
@@ -125,4 +125,50 @@ select -module dffe_01 -assert-count 0 t:\\pdk_icg
 select -module dffe_10 -assert-count 0 t:\\pdk_icg
 select -module dffe_11 -assert-count 0 t:\\pdk_icg
 
+#------------------------------------------------------------------------------
+
+design -reset
+read_rtlil << EOT
+
+module \bad1
+  wire input 1 \clk
+  wire input 3 \d1
+  wire input 2 \en
+  wire output 4 \q1
+  cell $dffe $auto$ff.cc:266:slice$27
+    parameter \CLK_POLARITY 1
+    parameter \EN_POLARITY 1
+    parameter \WIDTH 1
+    connect \CLK \clk
+    connect \D \d1
+    connect \EN 1'1
+    connect \Q \q1
+  end
+end
+
+module \bad2
+  wire input 1 \clk
+  wire input 3 \d1
+  wire input 2 \en
+  wire output 4 \q1
+  cell $dffe $auto$ff.cc:266:slice$27
+    parameter \CLK_POLARITY 1
+    parameter \EN_POLARITY 1
+    parameter \WIDTH 1
+    connect \CLK 1'1
+    connect \D \d1
+    connect \EN \en
+    connect \Q \q1
+  end
+end
+
+EOT
+
+# Check we don't choke on constants
+clockgate -pos pdk_icg ce:clkin:clkout -tie_lo scanen
+select -module bad1 -assert-count 0 t:\\pdk_icg
+select -module bad2 -assert-count 0 t:\\pdk_icg
+
+#------------------------------------------------------------------------------
+
 # TODO test -tie_lo