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Merge pull request #3920 from zachjs/asgn-expr
sv: support assignments within expressions
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,73 @@ | ||
module top; | ||
integer x, y, z; | ||
task check; | ||
input integer a, b, c; | ||
assert (x == a); | ||
assert (y == b); | ||
assert (z == c); | ||
endtask | ||
always_comb begin | ||
x = 0; y = 0; z = 0; | ||
check(0, 0, 0); | ||
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||
// post-increment/decrement statements | ||
x++; | ||
check(1, 0, 0); | ||
(* bar *) y (* foo *) ++; | ||
check(1, 1, 0); | ||
z--; | ||
check(1, 1, -1); | ||
(* bar *) z (* foo *) --; | ||
check(1, 1, -2); | ||
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||
// pre-increment/decrement statements are equivalent | ||
++z; | ||
check(1, 1, -1); | ||
(* bar *) ++ (* foo *) z; | ||
check(1, 1, 0); | ||
--x; | ||
check(0, 1, 0); | ||
(* bar *) -- (* foo *) y; | ||
check(0, 0, 0); | ||
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||
// procedural pre-increment/decrement expressions | ||
z = ++x; | ||
check(1, 0, 1); | ||
z = ++ (* foo *) x; | ||
check(2, 0, 2); | ||
y = --x; | ||
check(1, 1, 2); | ||
y = -- (* foo *) x; | ||
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||
// procedural post-increment/decrement expressions | ||
// TODO: support attributes on post-increment/decrement | ||
check(0, 0, 2); | ||
y = x++; | ||
check(1, 0, 2); | ||
y = x--; | ||
check(0, 1, 2); | ||
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||
// procedural assignment expressions | ||
x = (y = (z = 99) + 1) + 1; | ||
check(101, 100, 99); | ||
x = (y *= 2); | ||
check(200, 200, 99); | ||
x = (z >>= 2) * 4; | ||
check(96, 200, 24); | ||
y = (z >>= 1'sb1) * 2; // shift is implicitly cast to unsigned | ||
check(96, 24, 12); | ||
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||
// check width of post-increment expressions | ||
z = (y = 0); | ||
begin | ||
byte w; | ||
w = 0; | ||
x = {1'b1, ++w}; | ||
check(257, 0, 0); | ||
assert (w == 1); | ||
x = {2'b10, w++}; | ||
check(513, 0, 0); | ||
assert (w == 2); | ||
end | ||
end | ||
endmodule |
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Original file line number | Diff line number | Diff line change |
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read_verilog -sv asgn_expr.sv | ||
proc | ||
sat -verify -prove-asserts -show-all |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only permitted within procedures." 1 | ||
read_verilog -sv <<EOF | ||
module top; | ||
integer x, y; | ||
assign x = y++; | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only permitted within procedures." 1 | ||
read_verilog -sv <<EOF | ||
module top; | ||
integer x; | ||
wire [++x:0] y; | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only permitted within procedures." 1 | ||
read_verilog -sv <<EOF | ||
module top; | ||
integer x; | ||
integer y = --x; | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only permitted within procedures." 1 | ||
read_verilog -sv <<EOF | ||
module top; | ||
integer x, y; | ||
assign x = (y = 1); | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only permitted within procedures." 1 | ||
read_verilog -sv <<EOF | ||
module top; | ||
integer x, y; | ||
assign x = (y += 2); | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1 | ||
read_verilog <<EOF | ||
module top; | ||
integer x, y; | ||
initial y = ++x; | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1 | ||
read_verilog <<EOF | ||
module top; | ||
integer x, y; | ||
initial y = x++; | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,7 @@ | ||
logger -expect error "Assignments within expressions are only supported in SystemVerilog mode." 1 | ||
read_verilog <<EOF | ||
module top; | ||
integer x, y; | ||
initial y = (x = 1); | ||
endmodule | ||
EOF |
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,15 @@ | ||
read_verilog -sv <<EOF | ||
module top; | ||
integer x, y; | ||
initial y = (x += 1); | ||
endmodule | ||
EOF | ||
design -reset | ||
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||
logger -expect error "syntax error, unexpected TOK_ID" 1 | ||
read_verilog <<EOF | ||
module top; | ||
integer x, y; | ||
initial y = (x += 1); | ||
endmodule | ||
EOF |
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